Patent application number | Description | Published |
20080283919 | SINGLE AND DOUBLE-GATE PSEUDO-FET DEVICES FOR SEMICONDUCTOR MATERIALS EVALUATION - Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes. In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode. Light of broad spectrum or specific wavelength may be used to alter electrical carrier densities in the region between the electrodes to further analyze the electrical properties of the material, or alternatively, the device can be used as a detector of light having a wavelength shorter than the bandgap wavelength of the Si surface. | 11-20-2008 |
20090217967 | POROUS SILICON QUANTUM DOT PHOTODETECTOR - Embodiments of the present invention provide a solar energy converter, which includes a silicon layer having at least two regions of a first and a second conductivity type that form a P-N junction, at least a portion of the silicon layer being porous, and pores in the portion of porous silicon containing a semiconductor material, the semiconductor material being different from silicon; and a first and a second electrode being placed at a bottom and a top surface of the silicon layer respectively. Methods of manufacturing the same are also provided. | 09-03-2009 |
20090242869 | SUPER LATTICE/QUANTUM WELL NANOWIRES - Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire. | 10-01-2009 |
20100006850 | BEOL COMPATIBLE FET STRUCTURE - This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration. | 01-14-2010 |
20100037939 | METHODS OF FABRICATING SOLAR CELL CHIPS - A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips. | 02-18-2010 |
20100075261 | Methods for Manufacturing a Contact Grid on a Photovoltaic Cell - Processes for fabricating a contact grid for a photovoltaic cell generally includes providing a photovoltaic cell having an antireflective coating disposed on a sun facing side, the photovoltaic cell comprising a silicon substrate having a p-n junction; soft stamping a pattern of a UV sensitive photoresist and/or polymer onto the antireflective coating; exposing the UV sensitive photoresist and/or polymer to ultraviolet radiation to cure the UV sensitive photoresist and/or polymer; etching the pattern to form openings in the antireflective coating that define the contact grid; stripping the UV sensitive photoresist and/or polymer; and depositing a conductive metal into the openings defined by the pattern. The metal based paste can be aluminum based, which can be annealed at a relatively low temperature. | 03-25-2010 |
20100078056 | OPTICAL TANDEM PHOTOVOLTAIC CELL PANELS - A solar energy conversion device comprises a vertical stack of at least two panels stacked in a hierarchy from an upper panel to a lower panel with each of the panels including a matching array of solar cells having a different energy bandgap from other panels of solar cells in the vertical stack of panels. Each panel in the vertical stack may be arranged with one of the panels having solar cells with a higher energy bandgap situated in the hierarchy and in the stack above others of the panels containing solar cells with a lower energy bandgap. The top surface of the device is adapted for receiving solar energy incident upon the uppermost panel. Each upper panel absorbs a fraction of sunlight with larger solar photon energies larger than the energy bandgap thereof and transmits solar photons with photon energies less than larger solar photon energies to a remaining one of the panels lower in the hierarchy and positioned lower in the stack. | 04-01-2010 |
20100083997 | QUANTUM WELL GaP/Si TANDEM PHOTOVOLTAIC CELLS - Two junction solar energy conversion devices, i.e. photovoltaic cells have a bottom silicon N+/P/P+ photovoltaic cell and an upper GaP N+/P/P+ photovoltaic cell containing quantum well layers which extend the wavelength range over which the GaP cell absorbs light. The quantum well layers are composed of materials other than Gallium Phosphide (GaP) and may be either pseudomorphic or metamorphic. Light trapping may be incorporated at the top surface of the GaP photovoltaic cell along with anti-reflective coatings, and light trapping may be incorporated on the bottom surface of the silicon cell. The bottom surface of the silicon photovoltaic cell is coated with a passivating dielectric layer and electrical contact to the silicon is made with conductive vias extending through the passivating layer. | 04-08-2010 |
20100083999 | TANDEM NANOFILM SOLAR CELLS JOINED BY WAFER BONDING - An energy conversion device comprises at least two thin film photovoltaic cells fabricated separately and joined by wafer bonding. The cells are arranged in a hierarchical stack of decreasing order of their energy bandgap from top to bottom. Each of the thin film cells has a thickness in the range from about 0.5 μm to about 10 μm. The photovoltaic cell stack is mounted upon a thick substrate composed of a material selected from silicon, glass, quartz, silica, alumina, ceramic, metal, graphite, and plastic. Each of the interfaces between the cells comprises a structure selected from a tunnel junction, a heterojunction, a transparent conducting oxide, and an alloying metal grid; and the top surface and/or the lower surface of the energy conversion device may contain light-trapping means. | 04-08-2010 |
20100218813 | SILICON WAFER BASED STRUCTURE FOR HETEROSTRUCTURE SOLAR CELLS - A multi-junction photovoltaic device includes a silicon substrate and a dielectric layer formed on the silicon substrate. A germanium layer is formed on the dielectric layer. The germanium includes a crystalline structure that is substantially similar to the crystalline structure of the silicon substrate. A first photovoltaic sub-cell includes a first plurality of doped semiconductor layers formed on the germanium layer. At least a second photovoltaic sub-cell includes a second plurality of doped semiconductor layers formed on the first photovoltaic sub-cell that is on the germanium layer that is on the dielectric layer. | 09-02-2010 |
20100304519 | METHOD OF FABRICATING SOLAR CELL CHIPS - A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips. | 12-02-2010 |
20100317148 | METHODS FOR MANUFACTURING A CONTACT GRID ON A PHOTOVOLTAIC CELL - Processes for fabricating a contact grid for a photovoltaic cell generally includes providing a photovoltaic cell having an antireflective coating disposed on a sun facing side, the photovoltaic cell comprising a silicon substrate having a p-n junction; soft stamping a pattern of a UV sensitive photoresist and/or polymer onto the antireflective coating; exposing the UV sensitive photoresist and/or polymer to ultraviolet radiation to cure the UV sensitive photoresist and/or polymer; etching the pattern to form openings in the antireflective coating that define the contact grid; stripping the UV sensitive photoresist and/or polymer; and depositing a conductive metal into the openings defined by the pattern. The metal based paste can be aluminum based, which can be annealed at a relatively low temperature. | 12-16-2010 |
20110212622 | SURFACE TEXTURING USING A LOW QUALITY DIELECTRIC LAYER - A low cost method is described for forming a textured Si surface such as for a solar cell which includes forming a dielectric layer containing pinholes, anisotropically etching through the pinholes to form inverted pyramids in the Si surface and removing the dielectric layer thereby producing a high light trapping efficiency for incident radiation. | 09-01-2011 |
20110272009 | METHOD AND STRUCTURE OF PHOTOVOLTAIC GRID STACKS BY SOLUTION BASED PROCESSES - A grid stack structure of a solar cell, which includes a silicon substrate, wherein a front side of the silicon is doped with phosphorus to form a n-emitter and a back side of the silicon is screen printed with aluminum (Al) metallization; a dielectric layer, which acts as an antireflection coating (ARC), applied on the silicon; a mask layer applied on the front side to define a grid opening of the dielectric layer, wherein an etching method is applied to open an unmasked grid area; a light-induced plated nickel or cobalt layer applied to the front side with electrical contact to the back side Al metallization; a silicide layer formed by rapid thermal annealing of the plated nickel (Ni) or cobalt (Co); an optional barrier layer electrodeposited on the silicide; a copper (Cu) layer electrodeposited on the silicide/barrier film layer; and a thin protective layer is chemically applied or electrodeposited on top of the Cu layer. | 11-10-2011 |
20110278172 | ELECTRODEPOSITION UNDER ILLUMINATION WITHOUT ELECTRICAL CONTACTS - A method of forming patterned metallization by electrodeposition under illumination without external voltage supply on a photovoltaic structure or on n-type region of a transistor/junction. | 11-17-2011 |
20120031454 | EFFICIENT NANOSCALE SOLAR CELL AND FABRICATION METHOD - A photovoltaic device and method include a substrate layer having a plurality of structures including peaks and troughs formed therein. A continuous photovoltaic stack is conformally formed over the substrate layer and extends over the peaks and troughs. The photovoltaic stack has a thickness of less than one micron and is configured to transduce incident radiation into current flow. | 02-09-2012 |
20120031476 | COMPOSITIONALLY-GRADED BAND GAP HETEROJUNCTION SOLAR CELL - A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers. The photovoltaic device provides an open circuit voltage comparable to that of the first semiconductor material, and a short circuit current comparable to that of the second semiconductor material, thereby increasing the efficiency of the photovoltaic device. | 02-09-2012 |
20120138132 | SILICON WAFER BASED STRUCTURE FOR HETEROSTRUCTURE SOLAR CELLS - A multi-junction photovoltaic device includes a silicon substrate and a dielectric layer formed on the silicon substrate. A germanium layer is formed on the dielectric layer. The germanium includes a crystalline structure that is substantially similar to the crystalline structure of the silicon substrate. A first photovoltaic sub-cell includes a first plurality of doped semiconductor layers formed on the germanium layer. At least a second photovoltaic sub-cell includes a second plurality of doped semiconductor layers formed on the first photovoltaic sub-cell that is on the germanium layer that is on the dielectric layer. | 06-07-2012 |
20120174979 | Efficiency in Antireflective Coating Layers for Solar Cells - A solar cell includes a substrate having an N-region and a P-region, a first anti-reflective layer disposed on the substrate, a metallic contact disposed on the first anti-reflective layer, a second anti-reflective layer disposed on the first anti-reflective layer and the metallic contact, and a region partially defined by the first anti-reflective layer and the second anti-reflective layer having diffused metallic contact material operative to form a conductive path to the substrate through the first anti-reflective layer, the metallic contact, and the second anti-reflective layer. | 07-12-2012 |
20120285527 | LOW RESISTANCE, LOW REFLECTION, AND LOW COST CONTACT GRIDS FOR PHOTOVOLTAIC CELLS - The instant disclosure relates to contact grids for use in photovoltaic cells, wherein a cross-section of the contact grid fingers is shaped as a trapezoid, as well as a method of making photovoltaic cells comprising these contact grids. The contact grids of the instant disclosure are cost effective and, due to their thick metal grids, exhibit minimum resistance. Despite having thick metal grids, the unique shape of the contact grid fingers of the instant disclosure allow the photovoltaic cells in which they are employed to retain more solar energy than traditional solar cells by reflecting incoming solar energy back onto the surface of the solar cell instead of reflecting this energy away from the cell. | 11-15-2012 |
20120286236 | SUPER LATTICE/QUANTUM WELL NANOWIRES - Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire. | 11-15-2012 |
20120305929 | BEOL COMPATIBLE FET STRUCTRURE - This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration. | 12-06-2012 |
20130056043 | OPTICAL TANDEM PHOTOVOLTAIC CELL PANELS - A solar energy conversion device comprises a vertical stack of at least two panels stacked in a hierarchy from an upper panel to a lower panel with each of the panels including a matching array of solar cells having a different energy bandgap from other panels of solar cells in the vertical stack of panels. Each panel in the vertical stack may be arranged with one of the panels having solar cells with a higher energy bandgap situated in the hierarchy and in the stack above others of the panels containing solar cells with a lower energy bandgap. The top surface of the device is adapted for receiving solar energy incident upon the uppermost panel. Each upper panel absorbs a fraction of sunlight with larger solar photon energies larger than the energy bandgap thereof. | 03-07-2013 |
20130183553 | BATTERY WITH SELF-PROGRAMMING FUSE - A useful lifetime of an energy storage device can be extended by providing a series connection of a battery cell and an self-programming fuse. A plurality of series connections of a battery cell and an self-programming fuse can then be connected in a parallel connection to expand the energy storage capacity of the energy storage device. Each self-programming fuse can be a strip of a metal semiconductor alloy material, which electromigrates when a battery cell is electrically shorted and causes increases in the amount of electrical current therethrough. Thus, each self-programming fuse is a self-programming circuit that opens once the battery cell within the same series connection is shorted. | 07-18-2013 |
20140000691 | INTEGRATION OF A TITANIA LAYER IN AN ANTI-REFLECTIVE COATING | 01-02-2014 |
20140000693 | INTEGRATION OF A TITANIA LAYER IN AN ANTI-REFLECTIVE COATING | 01-02-2014 |
20140103286 | INTEGRATED CIRCUIT TAMPER DETECTION AND RESPONSE - The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and at least one memory cell coupled to the at least one photovoltaic cell. When the at least one photovoltaic cell is exposed to radiation, the at least one photovoltaic cell generates a current that causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and a reactive material coupled to the at least one photovoltaic cell, wherein a current from the at least one photovoltaic cell triggers an exothermic reaction in the reactive material. | 04-17-2014 |
20140109961 | COMPOSITIONALLY-GRADED BAND GAP HETEROJUNCTION SOLAR CELL - A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers. The photovoltaic device provides an open circuit voltage comparable to that of the first semiconductor material, and a short circuit current comparable to that of the second semiconductor material, thereby increasing the efficiency of the photovoltaic device. | 04-24-2014 |
20150030283 | Concentrating Thin Film Absorber Device and Method of Manufacture - An absorber device comprises a substrate; one or more thin film radiation absorbers arranged on the substrate; an integrated optical system, comprising at least one first optical element; a cover medium arranged above the substrate and the one or more radiation absorbers. The at least one first optical element and at least one corresponding one of the one or more radiation absorbers are aligned with respect to their optical axis, such that an incoming radiation is directed onto the one or more radiation absorbers by the optical system. A method of manufacturing an absorber device is also provided. | 01-29-2015 |
20150060856 | BEOL COMPATIBLE FET STRUCTURE - This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration. | 03-05-2015 |
20150072462 | TANDEM NANOFILM PHOTOVOLTAIC CELLS JOINED BY WAFER BONDING - An energy conversion device comprises at least two thin film photovoltaic cells fabricated separately and joined by wafer bonding. The cells are arranged in a hierarchical stack of decreasing order of their energy bandgap from top to bottom. Each of the thin film cells has a thickness in the range from about 0.5 μm to about 10 μm. The photovoltaic cell stack is mounted upon a thick substrate composed of a material selected from silicon, glass, quartz, silica, alumina, ceramic, metal, graphite, and plastic. Each of the interfaces between the cells comprises a structure selected from a tunnel junction, a heterojunction, a transparent conducting oxide, and an alloying metal grid; and the top surface and/or the lower surface of the energy conversion device may contain light-trapping means. | 03-12-2015 |