Patent application number | Description | Published |
20080251850 | PMD Liner Nitride Films and Fabrication Methods for Improved NMOS Performance - Semiconductor devices ( | 10-16-2008 |
20080268623 | SEMICONDUCTOR DOPING WITH IMPROVED ACTIVATION - A method is disclosed for doping a target area of a semiconductor substrate, such as a source or drain region of a transistor, with an electronically active dopant (such as an N-type dopant used to create active areas in NMOS devices, or a P-type dopant used to create active areas in PMOS devices) having a well-controlled placement profile and strong activation. The method comprises placing a carbon-containing diffusion suppressant in the target area at approximately 50% of the concentration of the dopant, and activating the dopant by an approximately 1,040 degree Celsius thermal anneal. In many cases, a thermal anneal at such a high temperature induces excessive diffusion of the dopant out of the target area, but this relative concentration of carbon produces a heretofore unexpected reduction in dopant diffusion during such a high-temperature thermal anneal. The disclosure also pertains to semiconductor components produced in this manner, and various embodiments and improvements of such methods for producing such components. | 10-30-2008 |
20080272097 | METHODOLOGY OF IMPROVING THE MANUFACTURABILITY OF LASER ANNEAL - A method of laser annealing a workpiece for reduction of warpage, slip defects and breakage, the method comprising (a) moving a workpiece through a laser beam in a x-axis first direction, (b) moving the workpiece in a y-axis second direction, (c) moving the workpiece through a laser beam in a minus x-axis first direction and repeating (a)-(c) until the workpiece is fully annealed in two successive laser annealing iterations. | 11-06-2008 |
20090004853 | METHOD FOR FORMING A METAL SILICIDE - The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing a metal layer on the substrate. The metal layer is annealed within a first temperature range and for a first dwell time of about 10 milliseconds or less to react at least a portion of the metal with the silicon to form a silicide. An unreacted portion of the metal is removed from the substrate. The silicide is annealed within a second temperature range for a second dwell time of about 10 milliseconds or less. | 01-01-2009 |
20090017588 | SYSTEMS AND METHODS THAT SELECTIVELY MODIFY LINER INDUCED STRESS - The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided ( | 01-15-2009 |
20090079010 | NICKEL SILICIDE FORMATION FOR SEMICONDUCTOR COMPONENTS - Semiconductor components are often fabricated that include a nickel silicide layer, e.g., as part of a gate electrode in a transistor component, which may be formed by forming a layer of nickel on a silicon-containing area of the semiconductor substrate, followed by thermally annealing the semiconductor substrate to produce a nickel silicide. However, nickel may tend to diffuse into silicon during the thermal anneal, and may form crystals that undesirably increase the sheet resistance in the transistor. Carbon may be placed with the nickel to serve as a diffusion suppressant and/or to prevent nickel crystal formation during thermal annealing. Methods are disclosed for utilizing this technique, as well as semiconductor components formed in accordance with this technique. | 03-26-2009 |
20090098665 | METHODOLOGY OF IMPLEMENTING ULTRA HIGH TEMPERATURE (UHT) ANNEAL IN FABRICATING DEVICES THAT CONTAIN SIGE - Exemplary embodiments provide methods for implementing an ultra-high temperature (UHT) anneal on silicon germanium (SiGe) semiconductor materials by co-implanting carbon into the SiGe material prior to the UHT anneal. Specifically, the carbon implantation can be employed to increase the melting point of the SiGe material such that an ultra high temperature can be used for the subsequent anneal process. Wafer warpage can then be reduced during the UHT anneal process and potential lithographic mis-alignment for subsequent processes can be reduced. Exemplary embodiments further provide an inline control method, wherein the wafer warpage can be measured to determine the litho-mis-alignment and thus to control the fabrication process. In various embodiments, the disclosed methods can be employed for the fabrication of source/drain extension regions and/or source/drain regions of transistor devices, and/or for the fabrication of base regions of bipolar transistors. | 04-16-2009 |
20090152639 | Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement - Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instabilty (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed. | 06-18-2009 |
20090170256 | ANNEALING METHOD FOR SIGE PROCESS - A method of forming a transistor comprising forming a gate structure over an n-type semiconductor body and forming recesses substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown in the recesses and a silicon cap layer is formed over the silicon germanium. Further introduction of impurities into the silicon germanium to increase the melting point thereof and implanting p-type source/drain regions in the semiconductor body is included in the method. The method concludes with performing a high temperature thermal treatment. | 07-02-2009 |
20090309140 | IN-SITU CARBON DOPED e-SiGeCB STACK FOR MOS TRANSISTOR - An integrated circuit containing a PMOS transistor with p-channel source/drain (PSD) regions which include a three layer PSD stack containing Si—Ge, carbon and boron. The first PSD layer is Si—Ge and includes carbon at a density between 5×10 | 12-17-2009 |
20100032727 | BORDER REGION DEFECT REDUCTION IN HYBRID ORIENTATION TECHNOLOGY (HOT) DIRECT SILICON BONDED (DSB) SUBSTRATES - Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed. | 02-11-2010 |
20100032813 | IC FORMED WITH DENSIFIED CHEMICAL OXIDE LAYER - A semiconductor device, such as an integrated circuit, has an oxide chemically grown on a silicon surface, and densified by annealing at, e.g., 950° C. for 4 to 5 seconds in an N | 02-11-2010 |
20100120215 | Nitrogen Based Implants for Defect Reduction in Strained Silicon - A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer. | 05-13-2010 |
20100159665 | CAPACITOR FORMED ON A RECRYSTALLIZED POLYSILICON LAYER - The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layer | 06-24-2010 |
20100210081 | STRESS MEMORIZATION DIELECTRIC OPTIMIZED FOR NMOS AND PMOS - A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors. | 08-19-2010 |
20110027953 | Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement - Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed. | 02-03-2011 |
20110120374 | System and Method for Mitigating Oxide Growth in a Gate Dielectric - Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric. | 05-26-2011 |
20130056811 | Hydrogen-Blocking Film for Ferroelectric Capacitors - An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH | 03-07-2013 |
20130309783 | HYDROGEN-BLOCKING FILM FOR FERROELECTRIC CAPACITORS - An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH | 11-21-2013 |