Patent application number | Description | Published |
20080220609 | Methods of Forming Mask Patterns on Semiconductor Wafers that Compensate for Nonuniform Center-to-Edge Etch Rates During Photolithographic Processing - Methods of forming integrated circuit devices include steps to selectively widen portions of a mask pattern extending adjacent an outer edge of a semiconductor wafer. These steps to selectively widen portions of the mask pattern are performed so that more uniform center-to-edge critical dimensions (CD) can be achieved when the mask pattern is used to support photolithographically patterning of underlying layers (e.g., insulating layers, antireflective coatings, etc.). | 09-11-2008 |
20080286698 | Semiconductor device manufacturing methods - Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. An additional substance is introduced and the lower portion of the masking material is patterned. The masking material and the additional substance are used to pattern the material layer of the workpiece. | 11-20-2008 |
20080305623 | Semiconductor device manufacturing methods - Methods for manufacturing semiconductor devices are disclosed. In a preferred embodiment, a method of processing a semiconductor device includes providing a workpiece, the workpiece comprising a material layer to be patterned disposed thereon. A hard mask is formed over the material layer. A first pattern is formed in the hard mask and an upper portion of the material layer using a first etch process. A second pattern is formed in the hard mask and the upper portion of the material layer using a second etch process, the second pattern being different than the first pattern. The first pattern and the second pattern are formed in a lower portion of the material layer using a third etch process and using the hard mask as a mask. | 12-11-2008 |
20090023078 | Lithography Masks and Methods of Manufacture Thereof - Lithography masks and methods of manufacture thereof are disclosed. For example, a method of manufacturing a lithography mask includes forming a stack over a substrate. The stack includes bottom attenuated phase shift material layers, intermediate opaque material layers, and finally top resist layers. The method further includes patterning the stack and then trimming the resist layers to uncover a portion of the opaque material layers. The uncovered opaque material layers are subsequently etched followed by removal of any remaining resist layers. | 01-22-2009 |
20090023259 | Method of Producing Non Volatile Memory Device - A method of forming a floating gate structure is disclosed, and includes modifying the etch chemistry of a plasma treated reactive ion etch process using an inert atom to physically damage a dielectric region. The damaged dielectric region is subsequently etched using a wet etch process. | 01-22-2009 |
20090081563 | Integrated Circuits and Methods of Design and Manufacture Thereof - Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features. | 03-26-2009 |
20100120177 | Feature Dimension Control in a Manufacturing Process - A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter. | 05-13-2010 |
20100283052 | Metrology Systems and Methods for Lithography Processes - Metrology systems and methods for lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A first semiconductor device is provided, and a layer of photosensitive material of the first semiconductor device is patterned with a plurality of corner rounding test features using the mask and a lithography process. An amount of corner rounding of the lithography process is measured by analyzing the plurality of corner rounding test features relative to other of the plurality of corner rounding test features formed on the layer of photosensitive material of the semiconductor device. The lithography process or the mask is altered in response to the amount of corner rounding measured, and a second semiconductor device is provided. The second semiconductor device is affected using the altered lithography process or the altered mask. | 11-11-2010 |
20110031563 | Method for Manufacturing a Semiconductor Device Having Doped and Undoped Polysilicon Layers - Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and forming a second polysilicon layer over a surface of the first polysilicon layer. Also, various illustrative embodiments of semiconductor devices are described that may be manufactured such as by the various methods described herein. | 02-10-2011 |
20110093823 | SEMICONDUCTOR INTER-FIELD DOSE CORRECTION - A method and apparatus are provided for adapting a semiconductor inter-field dose correction map from a first photolithography mask to a second photolithography mask using the same manufacturing stack and reactive ion etching processes, the method including: obtaining a first dose correction map for the first photolithography mask as a function of first chip or die identities; determining a first transformation matrix from the first chip or die identities of the first photolithography mask into an orthogonal coordinate system; determining a second transformation matrix from second chip or die identities of the second photolithography mask into the orthogonal coordinate system; and transforming the first dose correction map for the first photolithography mask into a second dose correction map for the second photolithography mask in correspondence with each of the first and second transformation matrices. | 04-21-2011 |
20110183266 | Semiconductor Device Manufacturing Methods - Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. A polymer material is disposed over the masking material. The masking material and the polymer layer are used to pattern the material layer of the workpiece. | 07-28-2011 |
20110250530 | Semiconductor Devices and Methods of Manufacturing Thereof - Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced. | 10-13-2011 |