Patent application number | Description | Published |
20100058146 | CHIEN-SEARCH SYSTEM EMPLOYING A CLOCK-GATING SCHEME TO SAVE POWER FOR ERROR CORRECTION DECODER AND OTHER APPLICATIONS - Chien search apparatus operative to evaluate an error locator polynomial having a known rank and including a sequence of terms for each element in a finite field whose elements correspond respectively to bits in each of a stream of data blocks to be decoded, the apparatus comprising a sequence of functional units each operative to compute a corresponding term in the sequence of terms included in the error locator polynomial, each term having a degree; and a power saving unit operative to de-activate at least one individual functional unit from among the sequence of functional units, the individual functional unit being operative, when active, to compute a term whose degree exceeds the rank. | 03-04-2010 |
20100064096 | SYSTEMS AND METHODS FOR TEMPORARILY RETIRING MEMORY PORTIONS - Flash memory apparatus including a plurality of memory portions, and a controller operative to reserve for data retention purposes, for at least a first duration of time, only certain portions from among said plurality of memory portions including allocating data, during the first duration of time, only to the certain portions, thereby to define at least one of the plurality of memory portions other than the certain portions as a retired memory portion for the first duration of time. | 03-11-2010 |
20100088557 | SYSTEMS AND METHODS FOR MULTIPLE CODING RATES IN FLASH DEVICES - A system and method for encoding information arriving from a host in order to store the coded information in flash memory, the method comprising encoding information arriving from a host for storage at a flash memory location including generating a number of redundancy bytes, the encoding proceeding at an encoding rate which is a function of the number of redundancy bytes generated, the encoding including determining an effective error rate, including an anticipated rate of expected reading errors, for the flash memory location; and selecting the encoding rate as a function of the effective error rate such that the number of redundancy bytes is sufficient to overcome the anticipated rate of expected reading errors with a predetermined degree of certainty. | 04-08-2010 |
20100095186 | REPROGRAMMING NON VOLATILE MEMORY PORTIONS - A system and a method for reprogramming a non volatile memory (NVM) portion, the method includes: receiving an initial content of an NVM portion; wherein the initial content differs from an erase content of the NVM portion; processing the previously programmed content in response to input content that should be represented by an initial content of the NVM portion; wherein the processing is characterized by a write limitation that prevents a non-erase value of a bit to be changed to an erase value; wherein the processing comprises at least one out of skip value based encoding, generating error correction information and error correction code based encoding; and writing the processed content of the NVM portion to the NVM portion. | 04-15-2010 |
20100122113 | SYSTEMS AND METHODS FOR HANDLING IMMEDIATE DATA ERRORS IN FLASH MEMORY - A flash memory system comprising temporary memory, writing apparatus for writing first logical data from the temporary memory into flash memory cells having at least two levels, thereby to generate a physical representation of the first logical data including known errors, reading apparatus for reading the physical representation from the cells, thereby to generate, and store in the temporary memory, second logical data which if read immediately is identical to the first logical data other than the known errors; and controlling apparatus controlling the writing apparatus and the reading apparatus and including known error ID apparatus operative to identify the known errors by comparing the first logical data to second logical data read immediately after the physical representation is generated, to store information characterizing the known errors and to use the information, when the second logical data is next read, to correct the known errors. | 05-13-2010 |
20100131806 | APPARATUS FOR CODING AT A PLURALITY OF RATES IN MULTI-LEVEL FLASH MEMORY SYSTEMS, AND METHODS USEFUL IN CONJUNCTION THEREWITH - A method and system for writing in flash memory, the system operative for, and the method comprising, writing data onto a plurality of logical pages characterized by a plurality of different probabilities of error respectively, the writing including encoding data intended for each of the plurality of physical pages using a redundancy code with a different code rate for each individual physical page, the code rate corresponding to the probability of error in the individual logical page. | 05-27-2010 |
20100131831 | LOW POWER CHIEN-SEARCH BASED BCH/RS DECODING SYSTEM FOR FLASH MEMORY, MOBILE COMMUNICATIONS DEVICES AND OTHER APPLICATIONS - A low power Chien searching method employing Chien search circuitry comprising at least two hardware components that compute at least two corresponding bits comprising a Chien search output, the method comprising activating only a subset of the hardware components thereby to compute only a subset of the bits of the Chien search output; and activating hardware components other than those in the subset of hardware components, to compute additional bits of the Chien search output other than the bits in the subset of bits, only if a criterion on the subset of the bits of the Chien search output is satisfied. | 05-27-2010 |
20100146192 | METHODS FOR ADAPTIVELY PROGRAMMING FLASH MEMORY DEVICES AND FLASH MEMORY SYSTEMS INCORPORATING SAME - A method for programming a plurality of data sequences into a corresponding plurality of flash memory functional units using a programming process having at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, the method comprising providing at least one indication of at least one varying situational characteristic and determining a value for said at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, for each flash memory functional unit, depending at least partly on said indication of said varying characteristic; and, for each individual flash memory functional unit from among said plurality of flash memory functional units, programming a sequence of bits into said individual flash memory functional unit using a programming process having at least one selectable parameter, said at least one selectable parameter being set at said value determined for said individual flash memory functional unit. | 06-10-2010 |
20100180073 | FLASH MEMORY DEVICE WITH PHYSICAL CELL VALUE DETERIORATION ACCOMMODATION AND METHODS USEFUL IN CONJUNCTION THEREWITH - A method for determining thresholds useful for converting cell physical levels into cell logical values in an array of digital memory cells storing physical levels which diminish over time, the method comprising determining extent of deterioration of the physical levels and determining thresholds accordingly for at least an individual cell in said array; and reading the individual cell including reading a physical level in the cell and converting the physical level into a logical value using the thresholds, wherein the determining comprises storing predefined physical levels rather than data-determined physical levels in each of a plurality of cells and computing extent of deterioration by determining deterioration of the predefined physical levels. | 07-15-2010 |
20100199149 | FLASH MEMORY APPARATUS AND METHODS USING A PLURALITY OF DECODING STAGES INCLUDING OPTIONAL USE OF CONCATENATED BCH CODES AND/OR DESIGNATION OF "FIRST BELOW" CELLS - A method for decoding a plurality of flash memory cells which are error-correction-coded as a unit, the method comprising providing a hard-decoding success indication indicating whether or not hard-decoding is at least likely to be successful; and soft-decoding the plurality of flash memory cells at a first resolution only if the hard-decoding success indication indicates that the hard-decoding is not at least likely to be successful. | 08-05-2010 |
20100211833 | SYSTEMS AND METHODS FOR AVERAGING ERROR RATES IN NON-VOLATILE DEVICES AND STORAGE SYSTEMS - A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks. | 08-19-2010 |
20100211856 | SYSTEMS AND METHODS FOR ERROR CORRECTION AND DECODING ON MULTI-LEVEL PHYSICAL MEDIA - Apparatus and methods for operating a flash device characterized by use of Lee distance based codes in a flash device so as to increase the number of errors that can be corrected for a given number of redundancy cells, compared with Hamming distance based codes. | 08-19-2010 |
20100253555 | ENCODING METHOD AND SYSTEM, DECODING METHOD AND SYSTEM - A decoder, an encoder, a decoding method and an encoding method are provided. The encoding method includes receiving data; generating a set of first codewords by applying a first encoding process on the received data; and performing a second encoding process on a folded version of each first codeword to provide a set of second codewords, wherein a folded version of a first codeword is representative of a storage of the first codeword in a two dimensional memory space, wherein the second codeword comprises redundancy bits. | 10-07-2010 |
20100293321 | SYSTEMS AND METHOD FOR FLASH MEMORY MANAGEMENT - A system and method for merging sectors of a flash memory module, the method includes: receiving multiple sectors, each received sector is associated with a current erase block out of multiple (L) erase blocks; accumulating the received sectors in a sector buffer, the sector buffer is stored in a non-volatile memory module; maintaining a merged sector map indicative of a sectors of the sector buffer that have been merged and sectors of the sector buffer waiting to be merged; finding a first sector waiting to be merged according to the merged sector map; merging the first sector and other sectors that belong to a same erase block as the first sector; and updating the merged sector map to indicate that that the first second and the other sectors that belonged to the same erase block were merged. | 11-18-2010 |
20110055461 | SYSTEMS AND METHODS FOR PRE-EQUALIZATION AND CODE DESIGN FOR A FLASH MEMORY - A system, computer readable program, and method for programming flash memory, the method includes: providing multiple pairs of most significant bit (MSB) page uncoded bit error rates (UBERs) and least significant bit (LSB) page UBERs; selecting a selected MSB page code rate and a selected LSB page code rate so that a selected MSB page UBER associated with the selected MSB page code rate and a selected LSB page UBER associated with the selected LSB page code rate support a highest average UBER out of the multiple pairs of MSB page UBERs and LSB page UBERs, wherein the selected MSB page code rate and the selected LSB page code rate are obtainable under a desired code rate constraint; and determining an encoding and programming scheme that may be based on the selected MSB page UBER, the selected MSB code rate, the selected LSB page UBER and the selected LSB code rate. | 03-03-2011 |
20110096612 | METHOD, SYSTEM, AND COMPUTER READABLE MEDIUM FOR READING AND PROGRAMMING FLASH MEMORY CELLS - A system, method and computer readable medium for programming and reading flash memory cells. Respective first and second read operations may be performed while supplying respective first and second bias voltage to multiple flash memory cells, to provide respective first and second read results, where the first bias voltage may be higher then the second bias voltage, and providing a read outcome that may be responsive to the first read results and to the second read results. A programming method may include performing first and second programming operations while supplying respective first and second bias voltages to multiple flash memory cells. The programming method may further include performing the first programming operation while programming information mapped to a highest least significant bit positive lobe, and performing the second programming operation while programming information mapped to at least one other least significant bit positive lobe. | 04-28-2011 |
20110119562 | SYSTEM AND METHOD FOR UNCODED BIT ERROR RATE EQUALIZATION VIA INTERLEAVING - A device, method, and computer readable medium for programming a codeword are presented. The method includes writing a first codeword portion to portions of nonvolatile memory rows, and writing a second codeword portion to portions of nonvolatile memory rows, wherein the first group of memory rows and the second group belong to non-overlapping groups. The device includes multiple nonvolatile memory rows, and a controller receiving a codeword comprising a first codeword portion and a second codeword portion. The controller writing the first codeword portion to portions of nonvolatile memory rows, and writing the second codeword portion to portions of nonvolatile memory rows, wherein the first group of nonvolatile memory rows differs and the second group of nonvolatile memory rows belong to non-overlapping groups, and the first and second groups of memory rows belong to multiple rows. A computer readable medium having stored thereon instructions performing methods described herein. | 05-19-2011 |
20110161775 | SYSTEM AND METHOD FOR SETTING A FLASH MEMORY CELL READ THRESHOLD - A system, method and computer readable medium for performing a first read attempt of multiple codeword portions while using a first read threshold candidate to provide multiple first read results, wherein the multiple codeword portions are stored in multiple flash memory cells; calculating a first read threshold candidate error correction decoding based score; wherein the calculating comprises error correction decoding of the multiple first read results; performing a second read attempt of the multiple codeword portions while using a second read threshold candidate to provide multiple second read results; calculating a second read threshold candidate error correction decoding based score; wherein the calculating comprises error correction decoding of the multiple second read results; and selecting a first read threshold out of the first and second read threshold candidates based on a relationship between the first and second read threshold candidate error correction decoding based scores. | 06-30-2011 |
20110214029 | SYSTEM AND METHOD FOR MULTI-DIMENSIONAL DECODING - A system and method for soft decoding data. A plurality of candidate error corrections may be generated to correct one or more data bits having soft bit information. Each candidate error correction may define suggested changes to the data bits and is associated with a soft bit value. The soft bit values associated the plurality of candidate error corrections may be mapped to a uniform scale, for example, a uniform finite or integer grid. The plurality of candidate error corrections may be ordered to have combined associated mapped values in a monotonically non-decreasing order. One or more of the plurality of candidate error corrections may be soft decoded in the order of the associated mapped values by a decoding operation for each candidate error correction therein with the associated non-mapped soft bit values. | 09-01-2011 |
20110214039 | SYSTEM AND METHOD FOR MULTI-DIMENSIONAL DECODING - A system and method for decoding data. Multi-dimensional encoded data may be received that potentially has errors. The multi-dimensional encoded data may encode each input bit in a set of input bits multiple times in multiple different dimensions to generate encoded bits. The encoded bits may be decoded in at least one of the multiple dimensions. If one or more errors are detected in a plurality of encoded bits in the at least one of the multiple dimensions, an intersection sub-set of the encoded data may be decoded that includes data encoding the same input bits encoded by the plurality of encoded bits in at least a second dimension of the multiple dimensions. The values of the input bits by decoding the intersection sub-set may be changed. | 09-01-2011 |
20110246792 | METHOD, SYSTEM AND MEDIUM FOR ANALOG ENCRYPTION IN A FLASH MEMORY - A system and method for analog encryption and decryption. A threshold level encryption key stream is generated and a programming level for each bit of a cipher data stream, with each bit having a one or zero state, is determined, where a threshold for distinguishing between the one or zero state for each bit varies based on a corresponding entry in the threshold level encryption key steam. Each bit of the cipher data stream in a cell of a memory is programmed based on the programming level. | 10-06-2011 |
20110252188 | SYSTEM AND METHOD FOR STORING INFORMATION IN A MULTI-LEVEL CELL MEMORY - A multi-level memory is used to store analog data by mapping a difference data using a mapping scheme that reduces the effect of errors caused by voltage level drift in the memory. | 10-13-2011 |
20110302428 | METHOD, SYSTEM AND MEDIUM FOR ANALOG ENCRYPTION IN A FLASH MEMORY - A system and method for analog encryption and decryption, in which the encryption and encoding processes are interrelated, such that by failing to decrypt the retrieved data, decryption fails. | 12-08-2011 |
20120005558 | SYSTEM AND METHOD FOR DATA RECOVERY IN MULTI-LEVEL CELL MEMORIES - A system and method are provided for data recovery in a multi-level cell memory device. One or more bits may be programmed sequentially in one or more respective levels of multi-level cells in the memory device. An interruption of programming a subsequent bit in a subsequent second or greater level of the multi-level cells may be detected. Data may be recovered from the multi-level cells defining the one or more bits programmed preceding the programming interruption of the second or greater level. | 01-05-2012 |
20120008401 | SYSTEMS AND METHODS FOR STORING, RETRIEVING, AND ADJUSTING READ THRESHOLDS IN FLASH MEMORY STORAGE SYSTEM - A method, system and computer-readable medium are provided for reading information from a memory unit. A request may be received to read information from a set of memory cells in the memory unit. At least one read threshold in an initial set of read thresholds may be perturbed to generate a perturbed set of read thresholds. The set of memory cells may be read using the perturbed set of read thresholds to provide a read result. The performance of said reading may be evaluated using the perturbed set of read thresholds. The at least one read threshold may be iteratively perturbed for each sequential read operation that the read performance is evaluated to be sub-optimal. | 01-12-2012 |
20120008414 | SYSTEMS AND METHODS FOR STORING, RETRIEVING, AND ADJUSTING READ THRESHOLDS IN FLASH MEMORY STORAGE SYSTEM - A method, system and computer-readable medium are provided for reading information from a memory unit. A read instruction may be received to read information from a set of memory cells in the memory unit. A data structure storing sets of read thresholds may be searched for a set of read thresholds based on one or more characteristic value(s) of the set of memory cells. If the set of read thresholds is found, the set of memory cells may be read to execute the read instruction using the found set of read thresholds. The set of read thresholds may be thresholds which were previously used to successfully read a set of cells having the same or similar characteristic value(s). | 01-12-2012 |
20120063227 | SYSTEM AND METHOD FOR ADJUSTING READ VOLTAGE THRESHOLDS IN MEMORIES - A system and method for adjusting read threshold voltage values, for example, in a read circuit internal to a memory device. The quality of an associated read result may be estimated for each read threshold voltage value used to read memory cells. Only read results estimated to have sufficient quality may be allowed to pass to storage. The read threshold voltage value may be adjusted for subsequent read operations, for example, if the associated read result is estimated to have insufficient quality. The read threshold voltage value may be iteratively adjusted, for example, until a read result is estimated to have sufficient quality. | 03-15-2012 |
20120066441 | SYSTEMS AND METHODS FOR AVERAGING ERROR RATES IN NON-VOLATILE DEVICES AND STORAGE SYSTEMS - A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks. | 03-15-2012 |
20120110250 | MEETHOD, SYSTEM AND COMPUTER READABLE MEDIUM FOR COPY BACK - Systems, computer readable media and methods for updating a flash memory device involve procedures for transferring, from a flash memory device to an external controller, only a portion of a data entity; and determining, by the external controller, based upon the portion of the data entity, whether to complete a copy back operation of the data entity or to correct errors of the data entity. If it is determined to correct errors of the data entity, then the procedure includes (a) completing a transfer of the data entity to the external controller; (b) error correcting the data entity to provide an amended data entity; and (c) writing the amended data entity to the flash memory device. If, however, it is determined to complete the copy back operation then the procedures includes completing the copy back operation of the data entity by transferring the data entity within the flash memory device. | 05-03-2012 |
20120144093 | INTERLEAVING CODEWORD PORTIONS BETWEEN MULTIPLE PLANES AND/OR DIES OF A FLASH MEMORY DEVICE - A system, a method and non-transitory computer readable medium storing instructions for interleaving at least two portions of a first codeword of the group between at least two flash memory planes while violating at least one ordering rule out of (a) an even odd ordering rule, (b) a programming type ordering rule, and (c) a codeword portions ordering rule and interleaving different portions of other codewords of the group between multiple flash memory planes while maintaining the even odd ordering rule, the programming type ordering rule and the codeword portions ordering rule. | 06-07-2012 |
20120216085 | DEVICES AND METHOD FOR WEAR ESTIMATION BASED MEMORY MANAGEMENT - A system, a non-transitory computer readable medium and a method for wear estimation of a flash memory device, the method may include: programming information to a first portion of the flash memory device during a test programming process; measuring a duration of the test programming process; and estimating a wear characteristic of the first portion of the flash memory device thereby providing an estimated wear characteristic, wherein the estimating is responsive to the duration of the test programming process. | 08-23-2012 |
20120236638 | OBTAINING SOFT INFORMATION USING A HARD INTERFACE - A flash memory controller, a computer readable medium and a method for generating reliability information using a hard information interface, the method may include performing multiple read attempts, while using the hard information interface, of a plurality of flash memory cells to provide multiple read results; wherein each flash memory cell is read by providing a reference voltage to the flash memory cell; wherein a same reference voltage is provided during the multiple read attempts; and generating, for each flash memory cell, reliability information based upon multiple read results of the flash memory cell. | 09-20-2012 |
20120311233 | SYSTEM AND METHOD FOR MANAGING A NON-VOLATILE MEMORY - A method, computer readable medium storing instructions and system for managing flash memory. Data sector are received and each is written into a data block of a buffer of a non-volatile memory device. Pointers in a data management structure are created for each data sector corresponding to an associated logical block and a storage location of the data sector in the buffer. When a predefined criterion is fulfilled before the buffer becomes full, a number of logical blocks to be merged is determined and data sectors corresponding to the number of logical blocks to be merged are written from the buffer to a primary non-volatile data storage memory of the non-volatile memory device. | 12-06-2012 |
20130080691 | FLASH MEMORY DEVICE WITH PHYSICAL CELL VALUE DETERIORATION ACCOMMODATION AND METHODS USEFUL IN CONJUNCTION THEREWITH - A method for converting a measured physical level of a cell into a logical value, in an array of memory cells storing physical levels which diminish over time, the method may include: determining extent of deterioration of the physical levels and determining thresholds accordingly for at least an individual cell in the array; and reading the individual cell including reading a physical level in said cell and converting said physical level into a logical value using at least some of said thresholds, wherein said determining extent of deterioration comprises storing predefined physical levels rather than data-determined physical levels in each of a plurality of cells and determining extent of deterioration by computing deterioration of said predefined physical levels. | 03-28-2013 |
20130104005 | FLASH MEMORY APPARATUS AND METHODS USING A PLURALITY OF DECODING STAGES INCLUDING OPTIONAL USE OF CONCATENATED BCH CODES AND/OR DESIGNATION OF "FIRST BELOW" CELLS - A method for decoding a plurality of flash memory cells which are error correction-coded, the method may include: comparing physical values residing in the plurality of flash memory cells to a first set of decision thresholds thereby to provide a first item of comparison information for each of the plurality of cells; comparing physical values residing the plurality of flash memory cells to a second set of decision thresholds, thereby to provide a second item of comparison information for each of the plurality of cells, wherein neither of the first and second sets of decision thresholds is a subset of the other; and determining logical values for the plurality of flash memory cells by combining said first and second items of comparison information. | 04-25-2013 |
20130212315 | STATE RESPONSIVEOPERATIONS RELATING TO FLASH MEMORY CELLS - A non-transitory computer readable medium, a flash controller and a method for state responsive encoding and programming; the method may include encoding an information entity by applying a state responsive encoding process to provide at least one codeword; wherein the state responsive encoding process is responsive to a state of flash memory cells; and programming the at least one codeword to at least one group of flash memory cells by applying a state responsive programming process that is responsive to the state, the state being either an estimated state or an actual state. | 08-15-2013 |
20130227207 | ADVANCED MANAGEMENT OF A NON-VOLATILE MEMORY - A method of managing a non-volatile memory device, the method comprising: receiving data sectors; writing each data sector into a data block that is allocated to a memory space subset that is associated with the data sector; wherein the data block belongs to a buffer of the non-volatile memory device; maintaining a management data structure that comprises location metadata about a location of each data sector in the buffer; and merging, if a criterion is fulfilled and before the buffer becomes full, data sectors stored at different data blocks and belong to a same set of logical memory blocks into a sequential portion of the non-volatile memory device, wherein the sequential portion differs from the buffer. | 08-29-2013 |
20140365847 | SYSTEMS AND METHODS FOR ERROR CORRECTION AND DECODING ON MULTI-LEVEL PHYSICAL MEDIA - Apparatus and methods for operating a flash device characterized by use of Lee distance based codes in a flash device so as to increase the number of errors that can be corrected for a given number of redundancy cells, compared with Hamming distance based codes. | 12-11-2014 |