Patent application number | Description | Published |
20080282107 | Method and Apparatus for Repairing Memory - Methods and apparatuses are disclosed in which a repair instruction, such as from a tester, causes an integrated circuit undergoing testing to substitute defective locations of a first set of memory cells in the integrated circuit with a second set of memory cells in the integrated circuit, despite the repair instruction omitting the defective locations of the first set of memory cells of the integrated circuit. | 11-13-2008 |
20090063918 | APPARATUS AND METHOD FOR DETECTING WORD LINE LEAKAGE IN MEMORY DEVICES - A method for detecting word line leakage in a memory device includes coupling a first plurality of word lines in the memory device to a voltage source while grounding a second plurality of word lines. Each of the second plurality of word lines is adjacent to a corresponding one of the first plurality of word lines. The method includes waiting for a period of time to allow the word lines to reach a predetermined read voltage level. The method also includes decoupling the first plurality of word lines from the voltage source and waiting for a second predetermined period of time to allow the first plurality of word lines to discharge. The method further includes sensing a current associated with the word lines, and comparing the current with a predetermined reference current which is selected for identifying a word line leakage condition associated with the first plurality of word lines. | 03-05-2009 |
20090201731 | Method and Apparatus for Accessing Memory With Read Error By Changing Comparison - In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such accesses to distinguish between logical levels. For example, the read bias arrangement and/or a read reference of a memory integrated circuit is changed. | 08-13-2009 |
20100061174 | Y-DECODER AND DECODING METHOD THEREOF - AY-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a third switch and a fourth switch coupled in parallel. The first switch and the second switch are respectively for receiving a first shielding voltage and a second shielding voltage. The third switch and the fourth switch are respectively for receiving a first sensing voltage and a second sensing voltage. | 03-11-2010 |
20100103738 | MEMORY AND OPERATING METHOD THEREOF - A method of programming data stored in a memory, which comprises a number of user-defined blocks, a number of manufacture-defined blocks, and an information block, includes the following steps. A programming address pointing to a user-defined block in the memory and programming data is obtained. After that, it is determined whether there is an empty manufacture-defined block among a number of user-defined blocks in the memory. If so, an information block in the memory is programmed to store the programming address and a replacing address pointing to the empty manufacture-defined block. The empty manufacture-defined block is programmed to store the programming data. | 04-29-2010 |
20100172191 | Voltage Regulation Method and Memory Applying Thereof - A voltage regulating method applied to a memory to regulate a word line voltage corresponding to a set of memory cells of the memory comprises the following steps. Firstly, a first value, which is for indicating an amount of data having a specific data value in a set of written data, is counted, wherein the set of written data is written into the set of memory cells. Next, a second value, which is for indicating an amount of data having the specific data value in a set of read data, is counted, wherein the set of read data is obtained by reading the set of written data. Then, a regulating voltage is determined according to a difference between the first and second values. After that, the word line voltage is regulated to be a sum of the word line voltage and the regulating voltage. | 07-08-2010 |
20110019456 | SENSE AMPLIFIER WITH SHIELDING CIRCUIT - A sense amplifier comprises a sense node, a reference node, a memory input stage circuit, a reference input stage circuit, an output stage circuit, and a shielding circuit. The memory input stage circuit comprises first input node for maintaining a first sense voltage established by a cell current and establishes a second sense voltage on the sense node in response to the first sense voltage. The reference input stage circuit comprises an output node and a second input node, which is for maintaining a first reference voltage established by the reference current and establishes a second reference voltage on the reference node in response to the first reference voltage. The output stage circuit obtains a sense result in response to the second reference voltage and the second sense voltage. The first shielding circuit shields the output node from being interfered with the second reference voltage on the reference node. | 01-27-2011 |
20110019487 | APPARATUS AND METHOD FOR DETECTING WORD LINE LEAKAGE IN MEMORY DEVICES - According to an embodiment of the present invention, a method for detecting word line leakage in a memory device includes coupling a first word line in the memory device to a voltage source while coupling a second word line in the memory device to a ground level voltage. Next, the first word line is decoupled from the voltage source. The method also includes comparing a current of the first word line with a predetermined reference current for determining a leakage condition of the word line. | 01-27-2011 |
20110058430 | Voltage Regulation Method and Memory Applying Thereof - A voltage regulating method applied to a memory to regulate a word line voltage corresponding to a set of memory cells of the memory comprises the following steps. Firstly, a first value, which is for indicating an amount of data having a specific data value in a set of written data, is counted, wherein the set of written data is written into the set of memory cells. Next, a second value, which is for indicating an amount of data having the specific data value in a set of read data, is counted, wherein the set of read data is obtained by reading the set of written data. Then, a regulating voltage is determined according to a difference between the first and second values. After that, the word line voltage is regulated to be a sum of the word line voltage and the regulating voltage. | 03-10-2011 |
20110060962 | Method and Apparatus for Accessing Memory With Read Error By Changing Comparison - In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such accesses to distinguish between logical levels. For example, the ratio of resistances characterizing input circuits of a sense amplifier and/or the read bias arrangement and/or a read reference of a memory integrated circuit is/are changed. | 03-10-2011 |
20110087838 | Memory Device and Operation Method Therefor - Provided is a MLC (Multi-level cell) memory device, comprising: a memory array, including a plurality of groups each storing a plurality of bits; and an inverse bit storage section, storing a first inverse bit data including a plurality of inverse bits, the plurality of bits in the same group in the memory array being related to a respective inverse bit. | 04-14-2011 |
20110122721 | Y-Decoder and Decoding Method Thereof - A Y-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a third switch and a fourth switch coupled in parallel. The first switch and the second switch are respectively for receiving a first shielding voltage and a second shielding voltage. The third switch and the fourth switch are respectively for receiving a first sensing voltage and a second sensing voltage. | 05-26-2011 |
20110133804 | CLOCK INTEGRATED CIRCUIT - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 06-09-2011 |
20110138213 | Clock Integrated Circuit - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 06-09-2011 |
20110138216 | Clock Integrated Circuit - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 06-09-2011 |
20110176378 | Memory Program Discharge Circuit - A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation. | 07-21-2011 |
20110210776 | Clock Integrated Circuit - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 09-01-2011 |
20120019232 | Current Source with Tunable Voltage-Current Coefficient - A current source providing an output current with a fixed current range includes a bias circuit, a resistor, a current mirror, and a controller. The bias circuit provides a first voltage weighted with a first tunable coefficient and a second voltage weighted with a second tunable coefficient. The resistor has a tunable resistance for determining a bias current according to a voltage difference between the first and the second voltages and the tunable resistance. The current mirror generates the output current according to the bias current. The controller adjusts the tunable resistance and one of the first and the second tunable coefficients to achieve a voltage-current coefficient with different values, while the bias current and the output current are kept within a fixed current range. | 01-26-2012 |
20120224443 | SENSE AMPLIFIER WITH SHIELDING CIRCUIT - A sense amplifier includes a first transistor, a second transistor, an output circuit, and a shielding circuit. The first transistor has a gate bias established by a cell current, and the second transistor has a gate bias established by a reference current. The output circuit is coupled to the first and the second transistor. The shielding circuit is located between the second transistor and the output circuit. | 09-06-2012 |
20120265923 | Program Method, Data Recovery Method, and Flash Memory Using the Same - A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed. | 10-18-2012 |
20120319756 | Clock Integrated Circuit - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 12-20-2012 |
20130100758 | LOCAL WORD LINE DRIVER - A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage reference signal, and an input signal. The word line driver has an output coupled to a word line. The control circuitry is configured to deselect the word line by applying the input signal to the input of the word line driver. For example, in a program operation the word line is deselected to indicate that the word line is not programmed, and another word line is selected to be programmed. During an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver. | 04-25-2013 |
20130107637 | Memory Program Discharge Circuit of Bit Lines With Multiple Discharge Paths | 05-02-2013 |
20130128672 | PROGRAM METHOD AND FLASH MEMORY USING THE SAME - A program method, applied in a flash memory, includes the following steps. Firstly, a first memory sector and a second memory sector are selected, wherein the first and the second memory sectors respectively correspond to a first word line and a second word line. Next, a first operation phase and a second operation phase are determined. Then, the first word line is biased with a first setup voltage, and the second word line is driven in one of a program operation and a program-verification operation, in the first operation phase. After that, the second word line is biased with a second setup voltage, and the first word line is driven in the other one of the program operation and the program-verification operation in the second operation phase. | 05-23-2013 |
20130148445 | LOCAL WORD LINE DRIVER - A memory circuit with a word line driver and control circuitry is disclosed. The plurality of word line drivers are coupled to a plurality of word lines. Word line drivers include a CMOS inverter, which can have an input and an output, and a p-type transistor and an n-type transistor. The output of the CMOS inverter is coupled to one of the plurality of word lines. The control circuitry has multiple modes, including at least a first mode to discharge a particular word line of the plurality of word lines via a first discharge path such as at least a first transistor type of the CMOS inverter; and a second mode to discharge the particular word line of the plurality of word lines via a second discharge path such as at least the a second transistor type of the CMOS inverter. | 06-13-2013 |
20130208552 | Method and Apparatus for Adjusting Drain Bias of A Memory Cell With Addressed and Neighbor Bits - The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window. | 08-15-2013 |
20130215687 | Method and Apparatus for Dynamic Sensing Window in Memory - A memory array is characterized by a threshold definition, which includes threshold voltage ranges representing data values stored by a part of the memory array, and a set of sense windows separating the threshold voltage ranges. The threshold definition is varied, responsive to at least one of program operations and erase operations. Such operations change a distribution of the data values stored in the memory group. | 08-22-2013 |
20130286744 | Bit Line Bias Circuit With Varying Voltage Drop - A bit line bias circuit of a memory architecture includes a varying voltage drop. In some embodiments, the voltage drop can depend on the threshold voltage of the memory cell selected to be read, or on the sense current flowing through the memory cell selected to be read. | 10-31-2013 |
20140055187 | CLOCK INTEGRATED CIRCUIT - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 02-27-2014 |
20140146611 | MEMORY DEVICE AND METHOD FOR PROGRAMMING MEMORY CELL OF MEMORY DEVICE - A method for programming a memory cell of a memory device includes the following steps. A plurality of cycle number ranges are set up. A specific one of the plurality of cycle number ranges, in which the memory cell having a drain terminal passes a program-verification, is determined. A bias voltage is applied to the drain terminal for programming the memory cell, wherein the bias voltage varies with the specific cycle number range. | 05-29-2014 |
20140269074 | MANAGEMENT OF NON-VOLATILE MEMORY - A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of sections, each section including at least one page, and each page including a plurality of memory cells. The method includes checking a current section of the plurality of sections against a damaged section table to determine whether the current section is damaged. The damaged section table records information about whether a section in the memory is good or damaged. The method further includes using the current section for programming if the current section is not damaged. | 09-18-2014 |
20140269127 | Memory Operation Latency Control - An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage. | 09-18-2014 |
20140281150 | DIFFERENCE L2P METHOD - A method for maintaining a data set includes storing a base copy of the data set in a first non-volatile memory having a first writing speed, storing changes to the data set in a first change data set in a second non-volatile memory having a second writing speed, and generating a current copy of the data set by reading the base copy and the changes. If a threshold number of entries in the first change data set is reached, then part or all of the first change data set is moved into a second change data set in the first non-volatile memory, where the generating step includes reading the second change data set. If a threshold number of entries in the second change data set is reached, then the current copy is generated by reading the base copy and the changes in the first and the second non-volatile memory. | 09-18-2014 |
20140281175 | Program Method, Data Recovery Method, and Flash Memory Using the Same - A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed. | 09-18-2014 |
20140361824 | CLOCK INTEGRATED CIRCUIT - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 12-11-2014 |
20150085588 | METHOD AND APPARATUS FOR ADJUSTING DRAIN BIAS OF A MEMORY CELL WITH ADDRESSED AND NEIGHBOR BITS - The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window. | 03-26-2015 |