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| 20140327132 | TSV Backside Reveal Structure and Exposing Process - A TSV backside reveal structure is provided, formed by a TSV conductive column on a substrate running throughout the substrate front surface and substrate back surface and stretching out of the substrate back surface; wherein, a sloping buffer is formed within the region between the substrate back surface and the TSV, and the height of the sloping buffer changes continuously; wherein the region close to the TSV has the highest height and the height of the buffer gradually decreases to that of the substrate back surface. | 11-06-2014 |
| 20140329381 | TSV Backside Reveal Structure and Exposing Process - A TSV exposing process is provided, including: performing a mechanical grinding process on the substrate back surface of a substrate with a TSV conductive column, a liner between the substrate and the TSV conductive column; performing a first and a second chemical mechanical polishing process on the grinded substrate back surface; then performing an etching on the substrate back surface, and making the TSV backside reveal more than 10 μm. | 11-06-2014 |
| 20150099423 | TSV Wafer Thinning Controlling Method and System - A TSV wafer thinning controlling method and system is provided, which can improve the accuracy of the wafer thinning technique. The system includes a chuck table used for carrying a wafer and a grinding device used for thinning the wafer; and further includes: an infrared sensor equipped on the chuck table or grinding device, and a measurement feedback system connected with the infrared sensor and the grinding device; wherein, the infrared sensor comprises an infrared emitting and receiving circuit, signal amplifying and filtering circuit and a data processor. | 04-09-2015 |
| 20150311093 | Method for Polishing a Polymer Surface - A method for polishing a polymer surface is provided by an embodiment of the present invention. The method includes: curing the polymer surface; polishing the polymer surface cured through a CMP process. By using the method for polishing a polymer surface provided by embodiments of the present invention, the mentioned problems in the prior art are solved. The uniformity of the polymer surface can be improved to <1% through a CMP process, which can meet the requirements of high density and small linewidth integration. | 10-29-2015 |
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| 20130046941 | WRITE CIRCUIT, READ CIRCUIT, MEMORY BUFFER AND MEMORY MODULE - The present invention provides a write circuit, a read circuit, a memory buffer and a memory module. The write circuit includes: a data collecting unit, a first check unit, a data restoring unit, a first check data generating unit, a first adjusting unit and a write unit; the read circuit includes: a data read unit, a second check unit, an output data generating unit, a second check data generating unit, a second adjusting unit and an output unit; the memory buffer includes the write circuit and the read circuit; the memory module includes the memory buffer and multiple memory chips connected to the memory buffer. Advantages of the present invention lie in that: data can be transmitted with a memory controller in a low power consumption manner, and the data transmitted based on conversion control data can be read out of or written into a DDR4 memory chip. | 02-21-2013 |
| 20130132660 | DATA READ/WRITE SYSTEM - The present invention provides a data read/write system. The data read/write system includes a memory controller and a memory module. The memory controller includes a first control circuit, a data output circuit, and a data receiving circuit. The memory module includes a memory buffer and at least two memory chips. The memory buffer includes a second control circuit, a write circuit, and a read circuit. The advantage of the present invention is that, when data is read or written into the memory chip, especially a DDR4 X4 memory chip, low power consumption of interface data transmission can be achieved through a data bus inversion control line DBI. | 05-23-2013 |
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| 20120263034 | METHOD, APPARATUS, AND SYSTEM FOR CONNECTING TO CALLED TERMINAL - A method for connecting to a called terminal includes: acquiring mobile station international integrated service digital network number (MSISDN) information corresponding to a called terminal which is located at an IP multimedia subsystem (IMS) domain, together with international mobile subscriber identity (IMSI) information and location area identity (LAI) information that correspond to the MSISDN information when a primary mobile access gateway control function entity mAGCF has a failure; and performing a connecting to the called terminal through a selected mAGCF according to the MSISDN information, the IMSI information and the LAI information. | 10-18-2012 |
| 20140308983 | CALLED RECOVERY METHOD, APPARATUS, AND SYSTEM - Embodiments of the present invention provide a called recovery method, including: receiving, by a target mobile switching center MSC, a provide roaming number PRN message sent by a backup MSC corresponding to a faulty MSC, where the PRN message carries an instruction for initiating paging to a called terminal through a mobility management entity MME; and performing international mobile subscriber identity IMSI paging according to the instruction, so that an MME to which a called terminal is attached controls the called terminal to perform circuit switched fallback CSFB to complete a called connection. Correspondingly, the embodiments of the present invention further provide a mobile switching center and a called recovery system. This solves a problem that in an MSC pool architecture, called paging in a CS domain cannot be performed when a terminal corresponding to a faulty MSC is attached to an E-UTRAN, and improves paging reliability. | 10-16-2014 |
| 20150271659 | METHOD AND APPARATUS FOR PROCESSING UNSTRUCTURED SUPPLEMENTARY SERVICE DATA SERVICE - The present invention discloses a method for processing USSD service. In this method, when an application server determines that a mobile terminal on a VoLTE network supports USSD operations over IMS, the application server sends an invite message to the mobile terminal, where the invite message includes an identifier of a USSD service; receives an invite response from the mobile terminal, where the invite response carries reply information entered by a subscriber and the identifier of the USSD service; generates, according to the reply information, a message that requests to execute the USSD service, where the message that requests to execute the USSD service carries the identifier of the USSD service; and sends, to a subscriber data server, the message that requests to execute the USSD service, so that the subscriber data server processes the USSD service. | 09-24-2015 |
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| 20090155977 | Methods for Forming a Gate and a Shallow Trench Isolation Region and for Planarizating an Etched Surface of Silicon Substrate - There is provide a method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, including the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. there are also provided a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region by improving the etching uniformity of sidewalls and bottom surface of the shallow trench, and a method for planarizating an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate. | 06-18-2009 |
| 20110300688 | METHODS FOR FORMING A GATE AND A SHALLOW TRENCH ISOLATION REGION AND FOR PLANARIZING AN ETCHED SURFACE OF SILICON SUBSTRATE - A method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, includes the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. The present invention further provides a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region, and a method for planarizing an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate. | 12-08-2011 |
| 20120273923 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND WAFER - A method of manufacturing semiconductor device and a wafer are provided in accordance with embodiments of the present invention, which relates to semiconductor technology. The method includes: providing a substrate, and forming a gate oxide layer and a polysilicon layer on a first surface of the substrate; etching the polysilicon layer by use of a patterned mask so as to form a polysilicon gate with reentrants; depositing a tensile stress film on a second surface of the substrate before etching the polysilicon layer. The tensile stress film can be deposited on the second surface of the substrate for generating the tensile stress for the wafer. Thus, a polysilicon gate with reentrants can be formed in etching process. In this way, semiconductor devices can have smaller gate-source/drain overlap capacitance and better TDDB parameters, and the performance of the devices can be improved. | 11-01-2012 |
| 20120276737 | POST-ETCHING TREATMENT PROCESS FOR COPPER INTERCONNECTING WIRES - A method for post-etching treatment of copper interconnecting wires that are used to electrically couple an upper interconnecting layer with a lower interconnecting layer includes forming the lower interconnecting layer on a substrate, and forming the upper interconnecting layer on the lower interconnecting layer. The lower interconnecting layer includes a first dielectric layer, a plurality of wire trenches formed in the first dielectric layer and being filled with copper, and a first top barrier layer overlying the first dielectric layer and the wire trenches. The upper interconnecting layer includes a second dielectric layer on the top barrier layer, and a plurality of vias extending through the second dielectric layer and the top barrier layer and exposing the copper in the wire trenches. The method further includes treating the exposed copper using a plasma process comprising NH | 11-01-2012 |
| 20120286370 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and method for manufacturing the same are disclosed. The method comprises: forming a gate insulating layer and a gate above a substrate; forming a spacer on both sides of the gate respectively; etching the substrate with the gate and spacers as mask to form indents; respectively forming a dummy sidewall on the side of the spacers opposite to the gate; etching substrate with the gate, spacers and dummy sidewalls as mask to form recesses which are deeper than the indents; removing the dummy sidewalls; and filling SiGe in the indents and recesses to form source/drain extent regions and source/drain regions of the semiconductor device; wherein before the step of filling SiGe, a step of heating the substrate to reflow the substrate material so as to at least change the shape of the side surface of the indent on the side close to the gate is implemented. | 11-15-2012 |
| 20120289017 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises placing a semiconductor substrate in an ashing chamber, the semiconductor substrate having a gate, a silicon nitride gate sidewall offset spacer or a silicon nitride gate sidewall pacer formed thereon, and a photo resist residue remaining on the semiconductor substrate, introducing a gas mixture including D | 11-15-2012 |
| 20120326328 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A method for manufacturing a semiconductor device includes providing a substrate having a first surface and a second surface, the second surface is on the opposite side of the substrate facing away from the first surface. The method further includes forming a first portion of an opening by etching a portion of the substrate from the first surface, forming a buffer layer on an inner surface of the first portion, etching a bottom of the buffer layer to expose an area of the underlying substrate, and etching the exposed area of the substrate to form a second portion of the opening. The method also includes performing an isotropic etching on the second portion of the opening to obtain a flask-shaped opening and filling the opening with a filling material. The method also includes partially removing a portion of the second surface and the filling material from the second portion of the opening. | 12-27-2012 |
| 20130168861 | ELECTRICALLY CONDUCTIVE DEVICE AND MANUFACTURING METHOD THEREOF - An electrically conductive device and a manufacturing method thereof are provided. According to the method, a protein tube portion and a conductor penetrating through the protein tube portion are formed on a graphene layer, and the conductor is in electrical contact with the graphene layer. A dummy dielectric material layer surrounding the protein tube portion can be formed on the graphene layer for support. The graphene layer can be protected from damage during the formation of the protein tube portion and the conductor because no etching process is employed in the formation. The method can facilitate the application of graphene in semiconductor devices as conductive interconnects. | 07-04-2013 |
| 20130171742 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a miniaturized semiconductor device so as to form MTJ elements therein include the steps of depositing a magnetic tunnel junction (MTJ) precursor layer on a substrate and planarizing the precursor layer; forming a sacrificial and patternable dielectric layer on the MTJ precursor layer; patterning the sacrificial dielectric layer in accordance with predetermined placements and shapes of a to-be-formed hard mask, the patterning forming corresponding openings in the sacrificial dielectric layer; depositing an etch-resistant conductive material such as Cu in the openings for example by way of plating, and selectively removing the sacrificial dielectric layer so as to leave behind the etch-resistant conductive material in the form of a desired hard mask. Using the hard mask to etch and thus pattern the MTJ precursor layer so as to form MTJ elements having desired locations, sizes and shapes. | 07-04-2013 |
| 20140332932 | SHALLOW TRENCH AND FABRICATION METHOD - Various embodiments provide shallow trenches and fabrication methods. In an exemplary method, a semiconductor substrate can be provided. A mask layer can be provided on the semiconductor substrate. An etch-cleaning process can be performed. The etch-cleaning process can include etching the semiconductor substrate to form a shallow trench by one or more etching steps using the mask layer as an etch mask. The etch-cleaning process can further include performing a plasma cleaning process after each of the one or more etching steps. The plasma cleaning process can use a plasma that is electronegative. | 11-13-2014 |
| 20140342559 | METHOD OF FORMING A SPACER PATTERNING MASK - The present disclosure pertains to a method of forming a spacer patterning mask. The method entails: providing a substrate; depositing, on the substrate, an interface layer, a core film and a first hard mask; patterning the core film and the first hard mask to form strips; depositing a spacer patterning layer to cover the core film and the first hard mask in the intermediate pattern; planarizing the spacer patterning layer by using the first hard mask in the intermediate pattern as a stop layer; etching the planarized spacer patterning layer; dry etching the second hard mask to expose the partially-etched spacer patterning layer; dry etching the exposed spacer patterning layer to form a spacer pattern; and removing the remaining first hard mask and second hard mask and the core film to obtain the final spacer patterning mask. | 11-20-2014 |
| 20150137370 | ELECTRICALLY CONDUCTIVE DEVICE AND MANUFACTURING METHOD THEREOF - An electrically conductive device and a manufacturing method thereof are provided. According to an exemplary embodiment, an electrically conductive device includes a graphene layer on a substrate, a protein tube portion on the graphene layer, and a conductor penetrating through the protein tube potion to the graphene layer, wherein the conductor is in electrical contact with the graphene layer. | 05-21-2015 |
| 20150187908 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Methods for fabricating semiconductor devices are provided. Gate structures are formed on a top surface of a substrate to form semiconductor devices. Trenches are formed in the substrate on both sides of each gate structure of each semiconductor device. The trenches on the both sides of each gate structure are filled with stress layers, the stress layers in the substrate protruding over the top surface of the substrate The stress layers are ion-doped and annealed on the both sides of each gate structure, and are pulse-etched to form a source region and a drain region of each gate structure. The pulse-etching is controlled such that the source regions and the drain regions of the plurality of semiconductor devices have a top surface coplanar with the top surface of the substrate. | 07-02-2015 |
| 20160086857 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD - The present disclosure provides a method for fabricating semiconductor devices. The method includes providing a substrate with a gate electrode film on the substrate and a gate electrode pattern film on the gate electrode film; forming at least one pattern layer on the gate electrode pattern film; and using the at least one pattern layer as the etch mask to etch portions of the gate electrode pattern film to expose portions of the gate electrode film and form a gate electrode pattern layer on the gate electrode film, the gate electrode pattern layer including a hard mask layer and a silicon layer, and sidewalls of the silicon layer in a direction perpendicular to a first direction having a first poly line width roughness. The method also includes performing an etch-repairing treatment on the sidewalls of the silicon layer in the direction perpendicular to the first direction. | 03-24-2016 |
| 20160087075 | TRANSISTOR DEVICE AND FABRICATION METHOD - The present disclosure provides a transistor device and fabrication method thereof. A dummy gate is formed on a substrate. An interlayer dielectric layer is formed on the substrate and sidewall surfaces of the dummy gate. The interlayer dielectric layer has a top surface coplanar with a top surface of the dummy gate. A mask layer is formed on the top surface of the interlayer dielectric layer. The mask layer is used as an etch mask to remove the dummy gate to form a trench in the interlayer dielectric layer to provide a trench footing on sidewall surfaces of the trench and near a trench bottom. The trench footing is then removed by applying a dry etching process. A gate electrode is then formed in the trench to form a transistor with improved electrical performance. | 03-24-2016 |
| 20160111329 | INTERCONNECT STRUCTURE AND FABRICATION METHOD THEREOF - A method for forming an interconnect structure is provided. The method includes providing a substrate with a surface; and forming a metal layer covering the surface of the substrate and with a desired grain size to reduce grain boundary scattering of the interconnect structure subsequently formed with the metal layer. The method also includes etching the metal layer to form a plurality of metal lines on the surface of the substrate and a plurality of metal pillars on each of the plurality of the metal lines of the interconnect structure; and forming a dielectric layer covering the surface of the substrate, surfaces of the metal lines, and side surfaces of the metal pillars. | 04-21-2016 |
| 20160111368 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD THEREOF - A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer; simultaneously forming a plurality of discrete first metal layers and openings by etching the initial metal layer; forming a plurality of sidewalls covering the side surface of the first metal layers; and forming a plurality of second metal layers to fill the openings. | 04-21-2016 |
| 20160118338 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF - A method for forming a semiconductor structure including providing a substrate; forming a dielectric layer covering a surface of the substrate; forming a plurality of first through holes exposing the surface of the substrate by etching the dielectric layer; forming first conductive vias by filling the plurality of first through holes using a first metal material and first conductive lines on the first conductive vias also using the first metal material; forming a plurality of second through holes exposing the surface of the substrate by etching the dielectric layer; and forming second conductive vias by filling the plurality of second through holes using a second metal material, different from the first metal material, and second conductive lines over the second conductive vias also using the second metal material, wherein the second metal material has a different anti-electromigration ability from the first metal material. | 04-28-2016 |
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| 20110276573 | JOURNAL EVENT CONSOLIDATION - Journal event consolidation extracts events occurring between two predetermined point in time on data volume, categorizes the events into categories of events, and consolidates the events in the categories of events. | 11-10-2011 |
| 20110282843 | METHOD AND SYSTEM FOR DATA BACKUP AND REPLICATION - A work flow is initiated and identified by a scenario identifier. A file system driver is notified to record operations on data associated with the work flow identified by the scenario identifier as raw journals without recording data content associated with the operations. The recorded operations are consolidated with previous operations as each operation is recorded in the raw journals. A system snapshot is initiated to be taken. The file system driver is notified of a point in time the system snapshot is taken. Data content associated with the consolidated recorded operations is retrieved from the system snapshot. A first packet is created from selected recorded operations and sent synchronously. A second packet including rest of the recorded operations along with associated data content are sent asynchronously with the point in time of the system snapshot. | 11-17-2011 |
| 20120136827 | PERIODIC DATA REPLICATION - Systems and methods for replicating data from a production server to a backup server include recording at least one operation on one or more data items stored in a volume of a production server. The operation may be recorded as at least one journal event in a memory. A determination may then be made regarding whether a system malfunction incident has occurred in the production server and if so, a first set of journal events may be transferred from the memory to an auxiliary storage at a first time instant. At a second time instant, a second set of journal events recorded in the memory between the first and second time instants may be transferred to the auxiliary storage. At one journal event stored in the auxiliary storage unit may then be sent for replication to a backup server. | 05-31-2012 |
| 20120197844 | BLOCK LEVEL DATA REPLICATION - Systems and methods for replicating data from a production server to a backup server include identifying one or more data blocks of a file that were modified after a first time instant and before a second time instant. The file may be associated with a protected directory of the production server. An representative data block (e.g., including a hash value) for at least one of the identified data blocks may be computed using a cryptography algorithm, e.g., MD | 08-02-2012 |
| 20130034960 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - The present invention discloses a method of fabricating a semiconductor device. In the present invention, after the formation of a photo-resist mask on a substrate, the photo-resist is subjected to a plasma pre-treatment, and then etch is conducted. With the plasma pre-treatment, a line width roughness of a linear pattern of the photo-resist can be improved, and thus much better linear patterns can be formed on the substrate during the subsequent etching steps. | 02-07-2013 |
| 20130034964 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The present invention discloses a method of manufacturing a semiconductor device. In order to form a trench with a smaller width, patterns of various monomers are formed by utilizing self-assembly characteristics of a block copolymer comprising various monomers. A metal or metal nitride is deposited on a surface of the block copolymer, the metal or metallic nitride selectively depositing due to a preferential chemical affinity between various monomers and the metal or metal nitride. After reaching a certain thickness, the metal or metal nitride layer begins to grow laterally. Deposition can be stopped by controlling deposition time so that the metal or metal nitride layer grows laterally but does not completely cover the surface of the block copolymer. Etching is then conducted using the metal or metal nitride layer as a mask to obtain a trench with a very small width. | 02-07-2013 |
| 20130054529 | SHADOW COPY BOOKMARK GENERATION - Systems and methods for generating a bookmark for a snapshot of one or more volumes of a production server include initiating a snapshot process to capture a shadow copy of a snapshot-volume set, which includes one or more volumes of the production server. The snapshot process (e.g., Volume Shadow Copy Service of Windows™ operating system) may include (a) temporarily freezing operations on a file system of the production server, and (b) releasing a freeze of operations on the file system of the production server. A bookmark for the shadow copy (representing a consistent state of the associated volumes) may be generated such that the bookmark corresponds to a completion of the temporarily freezing or releasing a freeze of the operations. The bookmark may include a point in time of the completion of the temporarily freezing or releasing the freeze of the operations. | 02-28-2013 |
| 20130059438 | METHOD FOR FORMING PATTERN AND MASK PATTERN, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A pattern formation method, mask pattern formation method and a method for manufacturing semiconductor devices are provided in this disclosure, which are directed to the field of semiconductor processes. The pattern formation method comprises: providing a substrate; forming a polymer thin film containing a block copolymer on the substrate; forming a first pattern through imprinting the polymer thin film with a stamp; forming domains composed of different copolymer components through directed self assembly of the copolymer in the first pattern; selectively removing the domains composed of copolymer components to form a second pattern. In the embodiments of the present invention, finer pitch patterns can be obtained through combining the imprinting and DSA process without exposure, which as compared to the prior art methods has the advantage of simplicity. Furthermore, stamps used in imprinting may have relative larger pitches, facilitating and simplifying the manufacture and alignment of the stamps. | 03-07-2013 |
| 20130073714 | System and Method for Data Set Synchronization and Replication - According to one embodiment of the present disclosure, a method for synchronizing data sets includes receiving a request to synchronize a first data set associated with a first server and a second data set associated with a second server. The method also includes determining, with reference to one or more replication constraints, whether to begin synchronization. The method further includes applying one or more resource control actions in response to determining to begin synchronization. | 03-21-2013 |
| 20130075811 | DOUBLE GATE TRANSISTOR AND METHOD OF FABRICATING THE SAME - The present invention discloses a double gate transistor and a method of fabricating said transistor, said transistor comprising: a semiconductor layer on a substrate; a fin structure formed in said semiconductor layer, said fin structure having two end portions for forming source and drain regions and a middle portion between said two end portions for forming a channel region, said middle portion including two opposed side surfaces perpendicular to a substrate surface; a first gate dielectric layer and a first gate disposed on one side surface of said middle portion; and a second gate dielectric layer and a second gate disposed on the other side surface of said middle portion. | 03-28-2013 |
| 20130095657 | POST-ETCH TREATING METHOD - This disclosure relates to a post-etch treating method. An opening is formed by etching a stacked structure of a dielectric layer, an intermediate layer and a metal hard mask layer arranged in order from bottom to top. The treating method sequentially comprises steps of: performing a first cleaning process on the stacked structure with the opening so as to remove at least a part of the metal hard mask layer; and performing a second cleaning process on the stacked structure with the opening so as to remove etching residues. | 04-18-2013 |
| 20130109175 | METHOD OF FABRICATING SEMICONDUCTOR DEVICES | 05-02-2013 |
| 20150213051 | SYSTEM AND METHOD FOR HIGH AVAILABILITY DATA REPLICATION - A data replication system and method is disclosed in which a master file server uses a first filter in a kernel space to intercept a file I/O events, send the file I/O events over a first network, for example a local area network, to a second filter in a kernel space of a first replica file server, and submit the file I/O event to a file system program in user space of the master file server to be processed. The second filter records the file I/O event in a memory of the second file server and sends an acknowledge message to the first filter indicating the file I/O event received by the second filter has been recorded in the replica file server. The first filter notifies user land in the first file server that the file I/O event has been processed if the first filter has received the acknowledge message and the file system program has completed processing the file I/O event in the first file server. In one embodiment, a data replication engine in the first replica file server replicates data stored in the first replica file server to a second replica file server in a location remote from the second replica file server, using a second network, for example a wide area network. | 07-30-2015 |
| 20150234712 | METHODS OF SYNCHRONIZING FILES INCLUDING SYNCHRONIZED HASH MAP LINKED LISTS AND RELATED DATA PROCESSING NODES - Synchronizing hard link files on master and replica servers includes providing master and replica server hard link file snapshots. The master server hard link file snapshot includes a listing of hard link file names from a root directory of the master server. The replica server hard link file snapshot includes a listing of hard link file names from a root directory of the replica server. The master server hard link file snapshot and the replica server hard link file snapshot are compared. A synchronized hash map linked list may be generated responsive to the comparison. The synchronized hash map linked list includes a listing of group identifications corresponding to physical data files at the master server. For each group identification in the synchronized hash map linked list, the synchronized hash map linked list includes at least a hard link file name from the root directory of the master server. | 08-20-2015 |
| 20150254080 | MODIFYING DISK IMAGES - A method includes identifying a first boot configuration type for a disk image. The disk image includes a master boot record and a disk partition. The disk partition comprises a volume boot record. The master boot record comprises first instructions for loading an operating system, and the volume boot record comprises second instructions for loading the operating system. The method further includes receiving an input indicative of a second boot configuration type. The method also includes modifying the disk image to use the second boot configuration type to load the operating system by modifying the first instructions and the second instructions. | 09-10-2015 |
