Patent application number | Description | Published |
20080211101 | Interlayer wiring of semiconductor device using carbon nanotube and method of manufacturing the same - Provided is an interlayer wiring structure of a semiconductor device using carbon nanotubes, and a method of manufacturing the interlayer wiring structure. The interlayer wiring structure is a carbon nanotube bundle that connects a first electrode to a second electrode. The carbon nanotube bundle includes a plurality of carbon nanotubes grown from a catalyst layer that is formed on a first electrode. The carbon nanotube bundle is made in a manner that a portion of the carbon nanotube bundle close to the second electrode has higher density of carbon nanotubes than another portion of the carbon nanotube bundle close to the first electrode. The carbon nanotube bundle is surrounded by an interlayer dielectric. In one embodiment of a method of manufacturing the carbon nanotube interlayer wire, liquid droplets are distributed between the carbon nanotubes to induce surface tension between the carbon nanotubes. The surface tension makes the carbon nanotube bundle maintain higher density of carbon nanotubes in a portion close to the second electrode. | 09-04-2008 |
20100074834 | APPARATUS AND METHOD FOR SURFACE-TREATING CARBON FIBER BY RESISTIVE HEATING - In an apparatus for surface-treating a carbon fiber, wherein the carbon fiber is heated by resistive heating, a carbon-containing gas is disposed on the carbon fiber, and carbon nanotubes are grown on a surface of the carbon fiber. | 03-25-2010 |
20130115420 | NANO COMPOSITE WITH SUPERHYDROPHOBIC SURFACE AND METHOD OF MANUFACTURING THE SAME - A nano composite with superhydrophobic surfaces including a bulk portion and a surface portion having a superhydrophobic pattern, wherein the bulk portion and the surface portion include the same material, and methods of manufacturing of the nano composite. | 05-09-2013 |
20130222510 | RESISTANCE HEATING COMPOSITION, HEATING COMPOSITE USING THE COMPOSITION, METHOD OF PREPARING THE HEATING COMPOSITE, AND HEATING APPARATUS AND FUSING APPARATUS USING THE SAME - A resistance heating composition including a silicon emulsion particle, a carbon nanotube, and an aqueous medium. | 08-29-2013 |
Patent application number | Description | Published |
20110044739 | FUSING DEVICE INCLUDING RESISTIVE HEATING LAYER AND IMAGE FORMING APPARATUS INCLUDING THE FUSING DEVICE - A fusing device includes; a heating member having a resistive heating layer constituting an outermost portion of the heating member, a nip forming member facing the heating member to form a fusing nip therewith, and a plurality of current supplying electrodes which contact an outer circumference of the resistive heating layer to supply electrical current to the resistive heating layer. | 02-24-2011 |
20110116850 | HEATING MEMBER INCLUDING RESISTIVE HEATING LAYER, AND FUSING APPARATUS AND IMAGE FORMING APPARATUS INCLUDING THE HEATING MEMBER - A heating member includes a resistive heating layer disposed on an outermost layer of the heating member, where the resistive heating layer comprises a conductive filler distributed in a base material and where the resistive heating layer emits heat when supplied with an electric current from an electrode, and a contacting unit which exposes the conductive filler of the resistive heating layer and contacts the electrode.. | 05-19-2011 |
20120181004 | SURFACE COATING LAYER AND HEAT EXCHANGER INCLUDING THE SURFACE COATING LAYER - A surface coating layer, in contact with a surface of a base material of a heat exchanger, comprises a plurality of composite layers comprising a first layer contacting a surface of the base material, the first layer comprising a first matrix and a first nanobody, and a second layer contacting a surface of the first layer and having an interface with the air, where the first layer and the second layer each include a different amount by volume of the first nanobody and the second nanobody, respectively. | 07-19-2012 |
20120207525 | RESISTANCE HEATING COMPOSITION AND HEATING COMPOSITE, HEATING APPARATUS, AND FUSING APPARATUS, INCLUDING RESISTANCE HEATING COMPOSITION - A resistance heating composition including carbon nanotubes, an ionic liquid, and a binder resin. | 08-16-2012 |
20120294659 | HEATING COMPOSITE, AND HEATING APPARATUS AND FUSING APPARATUS INCLUDING THE SAME - A heating composite, including a polymer matrix; and a carbon nanotube structure including a plurality of carbon nanotubes continuously connected to each other and integrated with the polymer matrix. | 11-22-2012 |
20130075632 | SUPERHYDROPHOBIC ELECTROMAGNETIC FIELD SHIELDING MATERIAL AND METHOD OF PREPARING THE SAME - A superhydrophobic electromagnetic field shielding material includes a curable resin and a carbon material, the superhydrophobic electromagnetic field shielding material including at least two depression patterns on an exposed surface. The at least two depression patterns may include a first depression pattern including a plurality of grooves having a same shape and a second depression pattern including a plurality of grooves having a same shape. The carbon material may be about 3 wt % to about 20 wt % based on the total weight of the superhydrophobic electromagnetic field shielding material. | 03-28-2013 |
20130112379 | SUPER-HYDROREPELLENT COATING COMPOSITION, SUPER-HYDROREPELLENT COATING LAYER INCLUDING CURED PRODUCT OF THE SUPER-HYDROREPELLENT COATING COMPOSITION, AND HEAT EXCHANGER INCLUDING THE SUPER-HYDROREPELLENT COATING LAYER - A super-hydrorepellent coating composition including a nano structure, polyorganosiloxane, a cross-linker, and a catalyst; a super-hydrorepellent coating layer including a cured product of the super-hydrorepellent coating composition; and a heat exchanger including the super-hydrorepellent coating layer. | 05-09-2013 |
20130251425 | HEATING MEMBER AND FUSING APPARATUS INCLUDING THE SAME - A heating member includes: a resistive heating layer which generates heat when supplied with electrical energy; a release layer as an outermost layer of the heating member and including a polymer; an intermediate layer disposed between the resistive heating layer and the release layer. The resistive heating layer includes a base polymer, and an electroconductive filler dispersed in the base polymer. The intermediate layer includes a polymer material being a same type as the base polymer of the resistive heating layer or the polymer of the release layer. | 09-26-2013 |
20130302074 | HEATING MEMBER AND FUSING APPARATUS INCLUDING THE SAME - A heating member for a fusing apparatus includes a resistive heating layer including a base polymer and an electroconductive filler dispersed in the base polymer, where the resistive heating layer generates heat by receiving electric energy, and where a storage modulus of the resistive heating layer is about 1.0 megapascal or greater. | 11-14-2013 |
20140021403 | CARBON NANOTUBE COMPOSITE AND METHOD OF MANUFACTURING THE SAME - A carbon nanotube includes carbon nanotubes, and an entanglement member which is combined with the carbon nanotubes and has a three-dimensional shape. | 01-23-2014 |
20140053393 | METHOD OF FORMING THIN RESISTIVE HEATING LAYER, HEATING MEMBER INCLUDING THE THIN RESISTIVE HEATING LAYER, AND FUSING UNIT INCLUDING THE HEATING MEMBER - A method of forming a thin film resistive heating layer, the method including: forming a polymer layer by extruding a polymer paste, in which an electrically conductive filler is dispersed, by using an extrusion molding operation, on an outer circumferential surface of a cylindrical member; and forming a thin film resistive heating layer by making an outer diameter of the polymer layer uniform by using a ring blading operation. | 02-27-2014 |
20140072353 | FUSING APPARATUS AND METHOD - A fusing apparatus including a heating unit including a heater having a substantially flat shape; a nip forming unit which faces the heating unit and forms a fusing nip with the heating unit; and a driving unit which moves the heating unit to alternately repeat a forward motion whereby the heating unit moves forward in a moving direction of the recording medium, when the fusing nip is formed, and a returning motion whereby the heating unit moves backward in a direction opposite to the moving direction of the recording medium, when the fusing nip is released. | 03-13-2014 |
20140126940 | HEATING MEMBER AND FUSING DEVICE INCLUDING THE SAME - A heating member includes: a resistive heating layer including: a medium-passing area, and non-medium-passing areas respectively on opposing sides of the medium-passing area at opposing side portions of the resistive heating layer; a core which supports the resistive heating layer; a thermally conductive layer between the resistive heating layer and the core, and disposed in a non-medium passing area at a side portion of the resistive heating layer; and an electrode which is between the resistive heating layer and the core, contacts the side portion of the resistive heating layer and supplies current to the resistive heating layer. A ratio of a contact area between the thermally conductive layer and the resistive heating layer to an area of the non-medium-passing area in which the thermally conductive layer is disposed, ranges from about 5% to about 25%. | 05-08-2014 |
20140205336 | RESISTANCE HEATING ELEMENT AND HEATING MEMBER AND FUSING DEVICE EMPLOYING THE SAME - A resistance heating element includes a positive temperature coefficient resistance heating layer having a positive temperature coefficient, and a negative temperature coefficient resistance heating layer, which is connected to the positive temperature coefficient resistance heating layer and has a negative temperature coefficient. | 07-24-2014 |
Patent application number | Description | Published |
20080261360 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a gate insulation layer is formed on a substrate including a first channel of a first conductive type and a second channel of a second conductive type different from the first conductive type. A first conductive layer including a first metal is formed on the gate insulation layer, and a second conductive layer including a second metal different from the first metal is formed on the first conductive layer formed over the second channel. The second conductive layer is partially removed by a wet etching process to form a second conductive layer pattern over the second channel. | 10-23-2008 |
20090283764 | TEG PATTERN FOR DETECTING VOID IN DEVICE ISOLATION LAYER AND METHOD OF FORMING THE SAME - Provided is a test element group (TEG) pattern for detecting a void in a device isolation layer. The TEG pattern includes active regions which are parallel to each other and extend in a first direction, a device isolation layer that separates the active regions, a first contact that is formed across the device isolation layer and a first one of the active regions that contacts a surface of the device isolation layer, and a second contact that is formed across the device isolation layer and a second one of the active regions that contacts another surface of the device isolation layer. | 11-19-2009 |
20090291568 | Semiconductor devices and method of forming the same - Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer. | 11-26-2009 |
20100025781 | Transistors with Multilayered Dielectric Films and Methods of Manufacturing Such Transistors - Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film. | 02-04-2010 |
20100167533 | METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer. | 07-01-2010 |
20100171182 | METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING SELECTIVE STRESS RELAXATION OF ETCH STOP LAYER - A strained semiconductor device includes a first plurality of transistors spaced with a first gate pitch, a second plurality of transistors spaced with a second gate pitch greater than the first gate pitch, and an etch stop layer disposed on the first and second pluralities of transistors. The etch stop layer between each of the second plurality of transistors has a greater proportion of a stress-altering material than the etch stop layer between each of the first plurality of transistors. | 07-08-2010 |
20110018044 | ETCH STOP LAYERS AND METHODS OF FORMING THE SAME - A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress layer disposed on the first stress layer, the first stress layer has a first stress and the second stress layer has a second stress, and the first stress is different from the second stress. | 01-27-2011 |
20110287622 | Transistors with Multilayered Dielectric Films and Methods of Manufacturing Such Transistors - Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film. | 11-24-2011 |
20110306171 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH DIFFERENTIALLY NITRIDED GATE INSULATORS - An insulation layer is formed on a substrate having an NMOS region and a PMOS region defined therein. A first conductive layer is formed on the insulation layer in the PMOS region, leaving a portion of the insulation layer in the NMOS region exposed. Nitriding is performed to produce a first nitrogen concentration in the insulation layer in the NMOS region and a second nitrogen concentration less than the first nitrogen concentration in the insulation layer in the PMOS region. A second conductive layer is formed on the insulation layer and the first conductive layer and the first and second conductive layers and the insulation layer are patterned to form a first gate structure and a second gate structure in the NMOS region and the PMOS region, respectively. | 12-15-2011 |
20110306184 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes: forming an epitaxial layer on a semiconductor substrate; forming a capping layer having a first thickness on the epitaxial layer; and oxidizing the capping layer in an oxygen atmosphere to form a first gate dielectric layer having a second thickness. | 12-15-2011 |
20120032332 | Semiconductor Devices Having A Diffusion Barrier Layer and Methods of Manufacturing the Same - Methods of manufacturing a semiconductor device include forming a gate insulation layer including a high-k dielectric material on a substrate that is divided into a first region and a second region; forming a diffusion barrier layer including a first metal on a second portion of the gate insulation layer in the second region; forming a diffusion layer on the gate insulation layer and the diffusion barrier layer; and diffusing an element of the diffusion layer into a first portion of the gate insulation layer in the first region. | 02-09-2012 |
20120034752 | METHODS OF FORMING A GATE STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - In a method of forming a gate structure, a gate pattern including a gate insulation layer pattern and a gate electrode sequentially stacked on a substrate is formed. The gate electrode includes a metal. A first plasma process is performed on the gate pattern using a reaction gas to reduce an oxidized edge portion of the gate electrode. The reaction gas includes nitrogen. A spacer is formed on a sidewall of the gate pattern. A threshold voltage is adjusted by reducing the oxidized edge portion of the gate electrode. Therefore, a semiconductor device including the gate pattern has excellent electrical characteristics. | 02-09-2012 |
20120070975 | Methods of Forming Gate Structure and Methods of Manufacturing Semiconductor Device Including the Same - A method of forming agate structure having an improved electric characteristic is disclosed. A gate insulating layer is formed on a substrate and a metal layer is formed on the gate insulating layer. Then, an amorphous silicon layer is formed on the metal layer by a physical vapor deposition (PVD) process. An impurity doped polysilicon layer is formed on the amorphous silicon layer. Formation of an oxide layer at an interface between the amorphous silicon layer and the metal layer may be prevented. | 03-22-2012 |
20120083111 | Methods of Manufacturing a Semiconductor Device - There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern. | 04-05-2012 |
20120309145 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Methods of manufacturing semiconductor devices include providing a substrate including a NMOS region and a PMOS region, implanting fluorine ions into an upper surface of the substrate, forming a first gate electrode of the NMOS region and a second gate electrode of the PMOS region on the substrate, forming a source region and a drain region in portions of the substrate, which are adjacent to two lateral surfaces of the first gate electrode and the second gate electrode, respectively, and performing a high-pressure heat-treatment process on an upper surface of the substrate by using non-oxidizing gas. | 12-06-2012 |
20140001606 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME | 01-02-2014 |
20140035050 | SEMICONDUCTOR DEVICES HAVING A DIFFUSION BARRIER LAYER AND METHODS OF MANUFACTURING THE SAME - Methods of manufacturing a semiconductor device include forming a gate insulation layer including a high-k dielectric material on a substrate that is divided into a first region and a second region; forming a diffusion barrier layer including a first metal on a second portion of the gate insulation layer in the second region; forming a diffusion layer on the gate insulation layer and the diffusion barrier layer; and diffusing an element of the diffusion layer into a first portion of the gate insulation layer in the first region. | 02-06-2014 |
20140141599 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes: forming an epitaxial layer on a semiconductor substrate; forming a capping layer having a first thickness on the epitaxial layer; and oxidizing the capping layer in an oxygen atmosphere to form a first gate dielectric layer having a second thickness. | 05-22-2014 |