Patent application number | Description | Published |
20080251880 | MIXED ORIENTATION AND MIXED MATERIAL SEMICONDUCTOR-ON-INSULATOR WAFER - The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed. | 10-16-2008 |
20090117694 | NANOWIRE BASED NON-VOLATILE FLOATING-GATE MEMORY - A non-volatile memory transistor with a nanocrystal-containing floating gate formed by nanowires is disclosed. The nanocrystals are formed by the growth of short nanowires over a crystalline program oxide. As a result, the nanocrystals are single-crystals of uniform size and single-crystal orientation. | 05-07-2009 |
20090289320 | FAST P-I-N PHOTODETECTOR WITH HIGH RESPONSITIVITY - A lateral p-i-n photodetector is provided that includes an array of vertical semiconductor nanowires of a first conductivity type that are grown over a semiconductor substrate also of the first conductivity type. Each vertically grown semiconductor nanowires of the first conductivity type is surrounded by a thick epitaxial intrinsic semiconductor film. The gap between the now formed vertically grown semiconductor nanowires-intrinsic semiconductor film columns (comprised of the semiconductor nanowire core surrounded by intrinsic semiconductor film) is then filled by forming an epitaxial semiconductor material of a second conductivity type which is different from the first conductivity type. In a preferred embodiment, the vertically grown semiconductor nanowires of the first conductivity type are n+ silicon nanowires, the intrinsic epitaxial semiconductor layer is comprised of intrinsic epitaxial silicon, and the epitaxial semiconductor material of the second conductivity type is comprised of p+ silicon. | 11-26-2009 |
20090293162 | MONOLITHIC HIGH ASPECT RATIO NANO-SIZE SCANNING PROBE MICROSCOPE (SPM) TIP FORMED BY NANOWIRE GROWTH - A scanning probe where the micromachined pyramid tip is extended by the growth of an epitaxial nanowire from the top portion of the tip is disclosed. A metallic particle, such as gold, may terminate the nanowire to realize an apertureless near-field optical microscope probe. | 11-26-2009 |
20090305454 | FAST P-I-N PHOTODETECTOR WITH HIGH RESPONSITIVITY - A lateral p-i-n photodetector is provided that includes an array of vertical semiconductor nanowires of a first conductivity type that are grown over a semiconductor substrate also of the first conductivity type. Each vertically grown semiconductor nanowires of the first conductivity type is surrounded by a thick epitaxial intrinsic semiconductor film. The gap between the now formed vertically grown semiconductor nanowires-intrinsic semiconductor film columns (comprised of the semiconductor nanowire core surrounded by intrinsic semiconductor film) is then filled by forming an epitaxial semiconductor material of a second conductivity type which is different from the first conductivity type. In a preferred embodiment, the vertically grown semiconductor nanowires of the first conductivity type are n+ silicon nanowires, the intrinsic epitaxial semiconductor layer is comprised of intrinsic epitaxial silicon, and the epitaxial semiconductor material of the second conductivity type is comprised of p+ silicon. | 12-10-2009 |
20090308844 | MONOLITHIC HIGH ASPECT RATIO NANO-SIZE SCANNING PROBE MICROSCOPE (SPM) TIP FORMED BY NANOWIRE GROWTH - A scanning probe where the micromachined pyramid tip is extended by the growth of an epitaxial nanowire from the top portion of the tip is disclosed. A metallic particle, such as gold, may terminate the nanowire to realize an apertureless near-field optical microscope probe. | 12-17-2009 |
20090311835 | NANOWIRE MOSFET WITH DOPED EPITAXIAL CONTACTS FOR SOURCE AND DRAIN - A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy. | 12-17-2009 |
20100047984 | SELF-ALIGNED METAL-SEMICONDUCTOR ALLOY AND METALLIZATION FOR SUB-LITHOGRAPHIC SOURCE AND DRAIN CONTACTS - A lateral double-gate FET structure with sub-lithographic source and drain regions is disclosed. The sub-lithographic source and drain regions are defined by a sacrificial spacer. Self-aligned metal-semiconductor alloy and metal contacts are made to the sub-lithographic source and drain using conventional silicon processing. | 02-25-2010 |
20100289744 | RFID-BASED INPUT DEVICE - A device for use with a computer system includes: an array of antennas for transmitting and receiving radio frequency signals; a portable unit operating within radio frequency range of the array of antennas, wherein a location of the portable unit is estimated by the radio frequency signals transmitted from the portable unit to a processor device. The device also includes storage for storing user identification. | 11-18-2010 |
20110133280 | DIFFERENT THICKNESS OXIDE SILICON NANOWIRE FIELD EFFECT TRANSISTORS - A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method performs an oxidation process simultaneously on the wires to form a first gate oxide on the first wire and a second gate oxide on the second wire. The first gate oxide is thicker than the second gate oxide. The method also forms gate conductors over the first gate oxide and the second gate oxide, forms sidewall spacers on the gate conductors, and dopes portions of the first wire and the second wire not covered by the sidewall spacers and the gate conductors to form source and drain regions within the first wire and the second wire. | 06-09-2011 |
20110241073 | STRUCTURE FOR SELF-ALIGNED SILICIDE CONTACTS TO AN UPSIDE-DOWN FET BY EPITAXIAL SOURCE AND DRAIN - A method for fabricating an upside-down p-FET includes: fully etching source and drain regions in a donor substrate by etching a silicon-on-insulator layer through buried oxide and partially etching the silicon substrate; refilling a bottom and sidewall surfaces of the etched source and drain regions with epitaxial silicide/germanide to form e-SiGe source and drain regions; capping the source and drain regions with self-aligning silicide/germanide; providing a silicide layer formed over the gate conductor line; providing a first stress liner over the gate and the e-SiGe source and drain regions; depositing a planarized dielectric over the self-aligning silicide/germanide; inverting the donor substrate; bonding the donor substrate to a host wafer; and selectively exposing the buried oxide and the e-SiGe source and drain regions by removing the donor wafer. | 10-06-2011 |
20110272673 | DIRECTIONALLY ETCHED NANOWIRE FIELD EFFECT TRANSISTORS - A method for forming a nanowire field effect transistor (FET) device includes depositing a first semiconductor layer on a substrate wherein a surface of the semiconductor layer is parallel to {110} crystalline planes of the semiconductor layer, epitaxailly depositing a second semiconductor layer on the first semiconductor layer, etching the first semiconductor layer and the second semiconductor layer to define a nanowire channel portion that connects a source region pad to a drain region pad, the nanowire channel portion having sidewalls that are parallel to {100} crystalline planes, and the source region pad and the drain region pad having sidewalls that are parallel to {110} crystalline planes, and performing an anisotropic etch that removes primarily material from {100} crystalline planes of the first semiconductor layer such that the nanowire channel portion is suspended by the source region pad and the drain region pad. | 11-10-2011 |
20110278539 | GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS - A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming first and second nanowire channels connected at each end to semiconductor pads at first and second wafer regions, respectively, with second nanowire channel sidewalls being misaligned relative to a crystallographic plane of the semiconductor more than first nanowire channel sidewalls and displacing the semiconductor toward an alignment condition between the sidewalls and the crystallographic plane such that thickness differences between the first and second nanowire channels reflect the greater misalignment of the second nanowire channel sidewalls. | 11-17-2011 |
20110278543 | GENERATION OF MUTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS - A method of modifying a wafer having semiconductor disposed on an insulator is provided and includes establishing first and second regions of the wafer with different initial semiconductor thicknesses, forming pairs of semiconductor pads connected via respective nanowire channels at each of the first and second regions and reshaping the nanowire channels into nanowires each having a respective differing thickness reflective of the different initial semiconductor thicknesses at each of the first and second regions. | 11-17-2011 |
20110315953 | METHOD OF FORMING COMPOUND SEMICONDUCTOR - A method of forming a semiconductor is provided and includes patterning a pad and a nanowire onto a wafer, the nanowire being substantially perpendicular with a pad sidewall and substantially parallel with a wafer surface and epitaxially growing on an outer surface of the nanowire a secondary layer of semiconductor material, which is lattice mismatched with respect to a material of the nanowire and substantially free of defects. | 12-29-2011 |
20120037880 | Contacts for Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate stack around a portion of the nanowire, forming a capping layer on the gate stack, forming a spacer adjacent to sidewalls of the gate stack and around portions of nanowire extending from the gate stack, forming a hardmask layer on the capping layer and the first spacer, forming a metallic layer over the exposed portions of the device, depositing a conductive material over the metallic layer, removing the hardmask layer from the gate stack, and removing portions of the conductive material to define a source region contact and a drain region contact. | 02-16-2012 |
20120068150 | Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer. | 03-22-2012 |
20120090057 | PRODUCTION SCALE FABRICATION METHOD FOR HIGH RESOLUTION AFM TIPS - A method of fabricating high resolution atomic force microscopy (AFM) tips including a single semiconductor nanowire grown at an apex of a semiconductor pyramid of each AFM tip is provided. The semiconductor nanowire that is grown has a controllable diameter and a high aspect ratio, without significant tapering from the tip of the semiconductor nanowire to its base. The method includes providing an AFM probe including a semiconductor cantilever having a semiconductor pyramid extending upward from a surface of said semiconductor cantilever. The semiconductor pyramid has an apex. A patterned oxide layer is formed on the AFM probe. The patterned oxide layer has an opening that exposes the apex of the semiconductor pyramid. A single semiconductor nanowire is grown on the exposed apex of the semiconductor pyramid utilizing a non-oxidized Al seed material as a catalyst for nanowire growth. | 04-12-2012 |
20120146000 | Omega Shaped Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire, forming a first protective spacer adjacent to sidewalls of the first gate structure and over portions of the nanowire extending from the first gate structure, removing exposed portions of the nanowire left unprotected by the first spacer, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a first source region and a first drain region. | 06-14-2012 |
20120190155 | NANOWIRE MOSFET WITH DOPED EPITAXIAL CONTACTS FOR SOURCE AND DRAIN - A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy. | 07-26-2012 |
20120205626 | SEMICONDUCTOR CHIP WITH GRAPHENE BASED DEVICES IN AN INTERCONNECT STRUCTURE OF THE CHIP - A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device. | 08-16-2012 |
20120261643 | GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SiC FINS OR NANOWIRE TEMPLATES - Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed. | 10-18-2012 |
20120280204 | DIRECTIONALLY ETCHED NANOWIRE FIELD EFFECT TRANSISTORS - A nanowire field effect transistor (FET) device, includes a source region comprising a first semiconductor layer disposed on a second semiconductor layer, the source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, a drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the source region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, and a nanowire channel member suspended by the source region and the drain region, wherein nanowire channel includes the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. | 11-08-2012 |
20120280205 | Contacts for Nanowire Field Effect Transistors - A nanowire field effect transistor (FET) device includes a channel region including a silicon nanowire portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate stack disposed circumferentially around the silicon portion, a source region including the first distal end of the silicon nanowire portion, a drain region including the second distal end of the silicon nanowire portion, a metallic layer disposed on the source region and the drain region, a first conductive member contacting the metallic layer of the source region, and a second conductive member contacting the metallic layer of the drain region. | 11-08-2012 |
20120329217 | Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer. | 12-27-2012 |
20120331593 | PRODUCTION SCALE FABRICATION METHOD FOR HIGH RESOLUTION AFM TIPS - A method of fabricating high resolution atomic force microscopy (AFM) tips including a single semiconductor nanowire grown at an apex of a semiconductor pyramid of each AFM tip is provided. The semiconductor nanowire that is grown has a controllable diameter and a high aspect ratio, without significant tapering from the tip of the semiconductor nanowire to its base. The method includes providing an AFM probe including a semiconductor cantilever having a semiconductor pyramid extending upward from a surface of said semiconductor cantilever. The semiconductor pyramid has an apex. A patterned oxide layer is formed on the AFM probe. The patterned oxide layer has an opening that exposes the apex of the semiconductor pyramid. A single semiconductor nanowire is grown on the exposed apex of the semiconductor pyramid utilizing a non-oxidized Al seed material as a catalyst for nanowire growth. | 12-27-2012 |
20130017673 | GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS - A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming first and second nanowire channels connected at each end to semiconductor pads at first and second wafer regions, respectively, with second nanowire channel sidewalls being misaligned relative to a crystallographic plane of the semiconductor more than first nanowire channel sidewalls and displacing the semiconductor toward an alignment condition between the sidewalls and the crystallographic plane such that thickness differences between the first and second nanowire channels reflect the greater misalignment of the second nanowire channel sidewalls. | 01-17-2013 |
20130019351 | PRODUCTION SCALE FABRICATION METHOD FOR HIGH RESOLUTION AFM TIPS - A high resolution AFM tip is provided which includes an AFM probe including a semiconductor cantilever having a semiconductor pyramid extending upward from a surface of the semiconductor cantilever, the semiconductor pyramid having an apex. The AFM tip also includes a single Al-doped semiconductor nanowire on the exposed apex of the semiconductor pyramid, wherein the single Al-doped semiconductor nanowire is epitaxial with respect to the apex of the semiconductor pyramid. | 01-17-2013 |
20130112937 | Nanowire Field Effect Transistor Device - A method for forming a field effect transistor device includes forming a nanowire suspended above a substrate, forming a dummy gate stack on a portion of the substrate and around a portion of the nanowire, removing exposed portions of the nanowire, epitaxially growing nanowire extension portions from exposed portions of the nanowire, depositing a layer of semiconductor material over exposed portions of the substrate, the dummy gate stack and the nanowire extension portions, and removing portions of the semiconductor material to form sidewall contact regions arranged adjacent to the dummy gate stack and contacting the nanowire extension portions. | 05-09-2013 |
20130112938 | Nanowire Field Effect Transistor Device - A field effect transistor device includes a nanowire, a gate stack comprising a gate dielectric layer disposed on the nanowire, a gate conductor layer disposed on the dielectric layer and a substrate, and an active region including a sidewall contact portion disposed on the substrate adjacent to the gate stack, the side wall contact portion is electrically in contact with the nanowire. | 05-09-2013 |
20130175597 | NANOWIRE FLOATING GATE TRANSISTOR - A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer. | 07-11-2013 |
20130178019 | Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region. | 07-11-2013 |
20130335326 | RFID-Based Input Device - An input device for use with a computer system includes: a pad and a portable unit operating as a computer mouse. The pad includes: a first antenna providing power to the portable unit, a radio frequency transmitter, a radio frequency receiver, a data link between the pad and the computer system, and an array of radio frequency antennas used for tracking a location of the portable unit. The portable unit includes at least one mouse antenna reflecting the radio frequency signals from the pad. The reflected radio frequency signals are used to estimate a location of the portable unit with respect to the array of radio frequency antennas in the pad. | 12-19-2013 |
20140014904 | Replacement Contacts for All-Around Contacts - In one aspect, a FET device is provided. The FET device includes a substrate; a semiconductor material on the substrate; at least one gate on the substrate surrounding a portion of the semiconductor material that serves as a channel region of the device, wherein portions of the semiconductor material extending out from the gate serve as source and drain regions of the device, and wherein the source and drain regions of the device are displaced from the substrate; a planarizing dielectric on the device covering the gate and the semiconductor material; and contacts which extend through the planarizing dielectric and surround the source and drain regions of the device. | 01-16-2014 |
20140017890 | Replacement Contacts for All-Around Contacts - In one aspect, a method of forming contacts to source and drain regions in a FET device includes the following steps. A patternable dielectric is deposited onto the device so as to surround each of the source and drain regions. The patternable dielectric is exposed to cross-link portions of the patternable dielectric that surround the source and drain regions. Uncross-linked portions of the patternable dielectric are selectively removed relative to the cross-linked portions of the patternable dielectric, wherein the cross-linked portions of the patternable dielectric form dummy contacts that surround the source and drain regions. A planarizing dielectric is deposited onto the device around the dummy contacts. The dummy contacts are selectively removed to form vias in the planarizing dielectric which are then filled with a metal(s) so as to form replacement contacts that surround the source and drain regions. | 01-16-2014 |
20140051217 | GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SiC FINS OR NANOWIRE TEMPLATES - Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed. | 02-20-2014 |
20140141618 | PROCESSING FOR OVERCOMING EXTREME TOPOGRAPHY - A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy. | 05-22-2014 |
20140183637 | STRUCTURE FOR SELF-ALIGNED SILICIDE CONTACTS TO AN UPSIDE-DOWN FET BY EPITAXIAL SOURCE AND DRAIN - An upside-down p-FET is provided on a donor substrate. The upside-down p-FET includes: self-terminating e-SiGe source and drain regions; a cap of self-aligning silicide/germanide over the e-SiGe source and drain regions; a silicon channel region connecting the e-SiGe source and drain regions; buried oxide above the silicon channel region; and a gate controlling current flow from the e-SiGe source region to the e-SiGe drain region. | 07-03-2014 |
20140239254 | GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS - A system is provided and includes a wafer and a mask. The wafer includes a silicon-on-insulator (SOI) structure disposed on a buried oxide (BOX) layer and has a first region with a first SOI thickness and a second region with a second SOI thickness, the first and second SOI thicknesses being different from one another and sufficiently large such that respective pairs of SOI pads connected via respective nanowires with different thicknesses are formable therein. The mask covers one of the first and second regions and prevents a thickness change of the other of the first and second regions from having effect at the one of the first and second regions. | 08-28-2014 |