Patent application number | Description | Published |
20150058512 | DYNAMICALLY RESIZING DIRECT MEMORY ACCESS (DMA) WINDOWS - A dynamic DMA window mechanism can resize DMA windows dynamically by increasing one DMA window at the expense of reducing a neighboring DMA window. The dynamic DMA window mechanism can decide to dynamically resize DMA windows based on a request from a system administrator, based on a request by an operating system device driver for an I/O adapter, or based on a performance monitor determining such a resizing would benefit system performance. Once one DMA window has been increased by allocating a portion of a donor DMA window, device drivers for the I/O devices corresponding to the two windows are updated to reflect the new DMA window sizes. | 02-26-2015 |
20150058513 | DYNAMICALLY RESIZING DIRECT MEMORY ACCESS (DMA) WINDOWS - A dynamic DMA window mechanism can resize DMA windows dynamically by increasing one DMA window at the expense of reducing a neighboring DMA window. The dynamic DMA window mechanism can decide to dynamically resize DMA windows based on a request from a system administrator, based on a request by an operating system device driver for an I/O adapter, or based on a performance monitor determining such a resizing would benefit system performance. Once one DMA window has been increased by allocating a portion of a donor DMA window, device drivers for the I/O devices corresponding to the two windows are updated to reflect the new DMA window sizes. | 02-26-2015 |
20150095700 | ISOLATING A PCI HOST BRIDGE IN RESPONSE TO AN ERROR EVENT - Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is unable to function, the host computing device may include a redundant PCI communication path for maintaining communication between the system resources and the I/O devices after a first PHB experiences an unrecoverable error. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state so long as the first PHB is functioning normally. However, once the first PHB experiences an unrecoverable error, the second PHB is changed to the master state and assumes the responsibility for maintaining communication between the system resources and the I/O devices. | 04-02-2015 |
20150127969 | SELECTIVELY COUPLING A PCI HOST BRIDGE TO MULTIPLE PCI COMMUNICATION PATHS - Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is reset, the host computing device may include a PCI communication path for maintaining communication between the system resources and the I/O devices. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state. The host may monitor the errors generated by a plurality of master PHBs and select a master PHB that satisfies an error threshold. The second PHB (i.e., a servant PHB) and the selected master PHB are synchronized, and the second PHB is coupled to the PCI communication path between the master PHB and a PCI switch. The master PHB can then be reset while the second PHB maintains PCI communication between the host and the I/O devices. | 05-07-2015 |
20150127971 | SELECTIVELY COUPLING A PCI HOST BRIDGE TO MULTIPLE PCI COMMUNICATION PATHS - Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is reset, the host computing device may include a PCI communication path for maintaining communication between the system resources and the I/O devices. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state. The host may monitor the errors generated by a plurality of master PHBs and select a master PHB that satisfies an error threshold. The second PHB (i.e., a servant PHB) and the selected master PHB are synchronized, and the second PHB is coupled to the PCI communication path between the master PHB and a PCI switch. The master PHB can then be reset while the second PHB maintains PCI communication between the host and the I/O devices. | 05-07-2015 |
20150301966 | SHARING MESSAGE-SIGNALED INTERRUPTS BETWEEN PERIPHERAL COMPONENT INTERCONNECT (PCI) I/O DEVICES - A PCI function, such as a device driver, may request that additional MSI resources be allocated to an I/O device coupled to a PCI Host Bridge (PHB). However, there may not be any unallocated MSI resource remaining in the PHB. Instead, a hypervisor may request to borrow MSI resources assigned to other PCI functions in the system. For example, the PCI function requesting the additional MSI resources may ask for a certain number of MSI resources for a certain period of time e.g., a lease. The hypervisor then determines which of the other PCI functions (referred to as a loaning PCI functions) are willing to lend or loan their MSI resources. Once the MSI resources available for lease are known, the hypervisor informs the requesting PCI function of these resources which, in turn, binds the additional MSI resources to the I/O device. | 10-22-2015 |
20150301967 | SHARING MESSAGE-SIGNALED INTERRUPTS BETWEEN PERIPHERAL COMPONENT INTERCONNECT (PCI) I/O DEVICES - A PCI function, such as a device driver, may request that additional MSI resources be allocated to an I/O device coupled to a PCI Host Bridge (PHB). However, there may not be any unallocated MSI resource remaining in the PHB. Instead, a hypervisor may request to borrow MSI resources assigned to other PCI functions in the system. For example, the PCI function requesting the additional MSI resources may ask for a certain number of MSI resources for a certain period of time—e.g., a lease. The hypervisor then determines which of the other PCI functions (referred to as a loaning PCI functions) are willing to lend or loan their MSI resources. Once the MSI resources available for lease are known, the hypervisor informs the requesting PCI function of these resources which, in turn, binds the additional MSI resources to the I/O device. | 10-22-2015 |