Patent application number | Description | Published |
20120244212 | ENHANCED METHOD AND COMPOSITION FOR THE TREATMENT OF HIV+ TUBERCULOSIS PATIENTS WITH ANTI-RETROVIRAL DRUGS AND LIPOSOMAL ENCAPSULATION FOR DELIVERY OF REDUCED GLUTATHIONE - The invention is the use of a therapeutically effective amount of glutathione (reduced) in a liposome encapsulation for oral administration to improve symptoms of illnesses that are related to tuberculosis and HIV and more generally viruses and for the treatment and prevention of virus, particularly HHV-6 and EBV, which liposomal encapsulation of glutathione (reduced) is referred to as liposomal glutathione. The application references specifically reduced glutathione and its importance, and how to stabilize it effectively so it can be taken orally, and need not be refrigerated. New uses for tuberculosis are discussed. The combination is proposed of reduced glutathione and Highly Active Anti-Retroviral Therapy having at least one pharmaceutical composition selected from the group of Nucleoside/tide Reverse Transcriptase Inhibitors (NRTIs), Protease Inhibitors (PIs), and Non-nucleoside Reverse Transcriptase Inhibitors (NnRTIs), and further anti-tuberculosis drugs. | 09-27-2012 |
20130129815 | LIPOSOMAL FORMULATION FOR ORAL ADMINISTRATION OF GLUTATHIONE (REDUCED) VIA GEL CAPSULE - The invention is a composition administrable orally to provide systemic glutathione (reduced) and a method for providing systemic glutathione by oral administration of glutathione (reduced) in a liposome encapsulation in a gel cap. The administration of a therapeutically effective amount of oral liposomal glutathione (reduced) results in improvement of symptoms in disease states related to glutathione deficiency such as Parkinson's disease and cystic fibrosis. Compounds enhancing the effect of the liposomal glutathione are contemplated such as Selenium, EDTA, carbidopa, and levodopa. | 05-23-2013 |
20130177630 | ANTI-CANCER COMPOSITION AND METHOD UTILIZING 3-BP AND LIPOSOMAL REDUCED GLUTATHIONE - The invention proposes a method of treatment of cancers exhibiting a CD163 characteristic by a liposomally formulated reduced glutathione. | 07-11-2013 |
20130202681 | LIPOSOMALLY ENCAPSULATED REDUCED GLUTATHIONE FOR MANAGEMENT OF CANCER AND DISRUPTION OF CANCER ENERGY CYCLES - A method of treatment of cancer with a formulation of liposomally encapsulated glutathione, that is preferably used orally, increases the level of glutathione in tissues in order to prevent and reverse the metabolic changes in cells that results in the formation of the metabolic “fuel supply” that supports cancer cells, and without which the cells can die out. The method prevents the oxidative stress that damages normal support cells such as stromal fibroblast cells. By blocking the “fuel supply,” the invention can protect, prevent and reverse these cells from the steps of autophagy and mitophagy, that results in the cells decreasing the normal production of ATP for energy and using aerobic glycolysis for energy production. The use of oral liposomally encapsulated glutathione will maintain the presence and normal function of caveolin in fibroblast and other cells, thus preventing their conversion to autophagic tumor stromal cells. | 08-08-2013 |
20140023696 | TREATMENT FOR IDIOPATHIC PULMONARY FIBROSIS - The invention proposes a method of treatment of idiopathic pulmonary fibrosis by a liposomally formulated reduced glutathione. | 01-23-2014 |
20140141071 | ORALLY ADMINISTRABLE LIPOSOMALLY ENCAPSULATED REDUCED GLUTATHIONE, WITH N-O ENHANCING COMPOUNDS FOR REVERSAL AND PREVENTION OF OXIDATION OF CHOLESTEROL AND OF LOW DENSITY LIPOPROTEIN - The invention proposes the sure of reduced glutathione in a liposome (liposomal reduced glutathione) for the oral administration of a therapeutically effective amount to ameliorate the progression of vascular disease, including atherosclerosis, diabetes, hypertension, narrowing of arteries leading to decreased blood flow, ischemic events, and the formation of blood clots, abnormal platelet aggregation, and thrombotic events, by reducing the amount and effect of oxidized cholesterol, oxidized HDL and oxidized LDL. The invention also proposes combining liposomal encapsulated glutathione with statin drugs to improve the effect of lowering not only cholesterol but also the oxidized cholesterol as well as oxidized HDL and oxidized LDL. The invention also proposes combining liposomal encapsulated glutathione with CoQ10 as a therapy for vascular disease and management of side effects of statin therapy. | 05-22-2014 |
20140193485 | ORALLY ADMINISTRABLE LIPOSOMALLY ENCAPSULATED REDUCED GLUTATHIONE, WITH ACE INHIBITORS FOR REVERSAL AND PREVENTION OF OXIDATION OF CHOLESTEROL AND OF LOW DENSITY LIPOPROTEIN - The invention proposes the combination of reduced glutathione in a liposome (liposomal reduced glutathione) with a specified concentration of reduced glutathione within the liposome for the oral administration of a therapeutically effective amount to ameliorate the progression of vascular disease, including atherosclerosis, diabetes, hypertension, narrowing of arteries leading to decreased blood flow, ischemic events, and the formation of blood clots, abnormal platelet aggregation, and thrombotic events, by reducing the amount and effect of oxidized cholesterol, oxidized HDL and oxidized LDL. The invention also proposes combining liposomal encapsulated glutathione with ACE inhibitors in order to improve the effect of lowering not only cholesterol but also the oxidized cholesterol as well as oxidized HDL and oxidized LDL. The invention also proposes combining liposomal encapsulated glutathione with lisinopril in particular. | 07-10-2014 |
20140234397 | TREATMENT OF KLEBSIELLA PNEUMONIAE WITH LIPOSOMALLY FORMULATED GLUTATHIONE - The composition of the invention, liposomal glutathione, has been recently shown to have utility for having an antibiotic like effect on Klebsiella pneumonia cultures in vitro, and in vivo as demonstrated by efficacy in reducing by large multiples the presence of cultures of Klebsiella in rats in animal tests. Further, because the liposomal glutathione bolsters body defenses as well as appearing to have direct killing action, the propensity to create more and more resistant strains to antibiotic treatment is downgraded. | 08-21-2014 |
20140271816 | TREATMENT OF POTENTIAL PLATELET AGGREGATION WITH LIPOSOMALLY FORMULATED GLUTATHIONE AND CLOPIDOGREL - The composition of the invention, liposomal glutathione in combination with clopidogrel has utility for improving the efficacy of clopidogrel in preventing the aggregation of platelet that can lead to clotting. The prevention of platelet aggregation has widespread utilization in many cardiovascular conditions such as coronary artery narrowing and more consistent “antiplatelet” activity is found with the invention, the combination of clopidogrel and liposomal reduced glutathione. | 09-18-2014 |
20150030668 | LIPOSOMALLY ENCAPSULATED REDUCED GLUTATHIONE FOR MANAGEMENT OF CANCER, INCLUDING WITH OTHER PHARMACEUTICAL COMPOSITIONS - This invention proposes an agent to block the “fuel supply” that energizes cancer cell growth by protecting surrounding cells to the cancer, particularly stromal fibroblast cells. The invention disables the products of surrounding cells useable for energy conversion by the cancer cell thereby crippling the cell and disabling its growth process. This application describes the use of a formulation of liposomally encapsulated glutathione that is preferably used orally to increase the level of glutathione in tissues in order to prevent and reverse the metabolic changes in cells that results in the formation of the metabolic fuel that supports cancer cells and to prevent the oxidative stress that damages normal support cells such as fibroblasts and can prevent and reverse these cells from the steps of autophagy and mitophagy that results in the cells decreasing the normal mitochondrial production of ATP for energy and resorting to the use of aerobic glycolysis for energy production. The use of oral liposomally encapsulated glutathione will maintain the presence and normal function of caveolin in fibroblast and other cells, thus preventing their conversion to autophagic tumor stromal cells. By stopping the formation of autophagic cells, the production of the metabolic fuel needed by cancer cells is stopped, which results in the death of the cancer cells. Compositions using liposomally encapsulated glutathione and other compounds that enhance the favorable effects of liposomal glutathione on cancer disease are referenced. | 01-29-2015 |
20150366933 | TREATMENT OF KLEBSIELLA PNEUMONIAE WITH LIPOSOMALLY FORMULATED GLUTATHIONE - The composition of the invention, liposomal glutathione, has been recently shown to have utility for having an antibiotic like effect on | 12-24-2015 |
20150374626 | TREATMENT OF EVOLVING BACTERIAL RESISTANCE DISEASES INCLUDING KLEBSIELLA PNEUMONIAE WITH LIPOSOMALLY FORMULATED GLUTATHIONE - The composition of the invention, liposomal glutathione, has been recently shown to have utility for having an antibiotic like effect on | 12-31-2015 |
Patent application number | Description | Published |
20100332578 | Method and apparatus for performing efficient side-channel attack resistant reduction - A time-invariant method and apparatus for performing modular reduction that is protected against cache-based and branch-based attacks is provided. The modular reduction technique adds no performance penalty and is side-channel resistant. The side-channel resistance is provided through the use of lazy evaluation of carry bits, elimination of data-dependent branches and use of even cache accesses for all memory references. | 12-30-2010 |
20110153700 | Method and apparatus for performing a shift and exclusive or operation in a single instruction - Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value. | 06-23-2011 |
20110153993 | Add Instructions to Add Three Source Operands - A method in one aspect may include receiving an add instruction. The add instruction may indicate a first source operand, a second source operand, and a third source operand. A sum of the first, second, and third source operands may be stored as a result of the add instruction. The sum may be stored partly in a destination operand indicated by the add instruction and partly a plurality of flags. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium. | 06-23-2011 |
20110153994 | Multiplication Instruction for Which Execution Completes Without Writing a Carry Flag - A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium. | 06-23-2011 |
20110161635 | Rotate instructions that complete execution without reading carry flag - A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag. | 06-30-2011 |
20120151183 | ENHANCING PERFORMANCE BY INSTRUCTION INTERLEAVING AND/OR CONCURRENT PROCESSING OF MULTIPLE BUFFERS - An embodiment may include circuitry to execute, at least in part, a first list of instructions and/or to concurrently process, at least in part, first and second buffers. The execution of the first list of instructions may result, at least in part, from invocation of a first function call. The first list of instructions may include at least one portion of a second list of instructions interleaved, at least in part, with at least one other portion of a third list of instructions. The portions may be concurrently carried out, at least in part, by one or more sets of execution units of the circuitry. The second and third lists of instructions may implement, at least in part, respective algorithms that are amenable to being invoked by separate respective function calls. The concurrent processing may involve, at least in part, complementary algorithms. | 06-14-2012 |
20130227252 | Add Instructions to Add Three Source Operands - A method in one aspect may include receiving an add instruction. The add instruction may indicate a first source operand, a second source operand, and a third source operand. A sum of the first, second, and third source operands may be stored as a result of the add instruction. The sum may be stored partly in a destination operand indicated by the add instruction and partly a plurality of flags. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium. | 08-29-2013 |
20130275722 | METHOD AND APPARATUS TO PROCESS KECCAK SECURE HASHING ALGORITHM - A processor includes a plurality of registers, an instruction decoder to receive an instruction to process a KECCAK state cube of data representing a KECCAK state of a KECCAK hash algorithm, to partition the KECCAK state cube into a plurality of subcubes, and to store the subcubes in the plurality of registers, respectively, and an execution unit coupled to the instruction decoder to perform the KECCAK hash algorithm on the plurality of subcubes respectively stored in the plurality of registers in a vector manner. | 10-17-2013 |
20130283064 | METHOD AND APPARATUS TO PROCESS SHA-1 SECURE HASHING ALGORITHM - A processor includes an instruction decoder to receive a first instruction to process a SHA-1 hash algorithm, the first instruction having a first operand to store a SHA-1 state, a second operand to store a plurality of messages, and a third operand to specify a hash function, and an execution unit coupled to the instruction decoder to perform a plurality of rounds of the SHA-1 hash algorithm on the SHA-1 state specified in the first operand and the plurality of messages specified in the second operand, using the hash function specified in the third operand. | 10-24-2013 |
20130290285 | DIGEST GENERATION - In one embodiment, circuitry may generate digests to be combined to produce a hash value. The digests may include at least one digest and at least one other digest generated based at least in part upon at least one CRC value and at least one other CRC value. The circuitry may include cyclical redundancy check (CRC) generator circuitry to generate the at least one CRC value based at least in part upon at least one input string. The CRC generator circuitry also may generate the at least one other CRC value based least in part upon at least one other input string. The at least one other input string resulting at least in part from at least one pseudorandom operation involving, at least in part, the at least one input string. Many modifications, variations, and alternatives are possible without departing from this embodiment. | 10-31-2013 |
20130326201 | PROCESSOR-BASED APPARATUS AND METHOD FOR PROCESSING BIT STREAMS - An apparatus and method are described for processing bit streams using bit-oriented instructions. For example, a method according to one embodiment includes the operations of: executing an instruction to get bits for an operation, the instruction identifying a start bit address and a number of bits to be retrieved; retrieving the bits identified by the start bit address and number of bits from a bit-oriented register or cache; and performing a sequence of specified bit operations on the retrieved bits to generate results. | 12-05-2013 |
20140006536 | TECHNIQUES TO ACCELERATE LOSSLESS COMPRESSION | 01-02-2014 |
20140006753 | MATRIX MULTIPLY ACCUMULATE INSTRUCTION | 01-02-2014 |
20140013086 | ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS - A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register. | 01-09-2014 |
20140016773 | INSTRUCTIONS PROCESSORS, METHODS, AND SYSTEMS TO PROCESS BLAKE SECURE HASHING ALGORITHM - A method of an aspect includes receiving an instruction indicating a first source having at least one set of four state matrix data elements, which represent a complete set of four inputs to a G function of a cryptographic hashing algorithm. The algorithm uses a sixteen data element state matrix, and alternates between updating data elements in columns and diagonals. The instruction also indicates a second source having data elements that represent message and constant data. In response to the instruction, a result is stored in a destination indicated by the instruction. The result includes updated state matrix data elements including at least one set of four updated state matrix data elements. Each of the four updated state matrix data elements represents a corresponding one of the four state matrix data elements of the first source, which has been updated by the G function. | 01-16-2014 |
20140016774 | INSTRUCTIONS TO PERFORM GROESTL HASHING - A method is described. The method includes executing an instruction to perform one or more Galois Field (GF) multiply by 2 operations on a state matrix and executing an instruction to combine results of the one or more GF multiply by 2 operations with exclusive or (XOR) functions to generate a result matrix. | 01-16-2014 |
20140019693 | PARALLEL PROCESSING OF A SINGLE DATA BUFFER - Technologies for executing a serial data processing algorithm on a single variable length data buffer includes streaming segments of the buffer into a data register, executing the algorithm on each of the segments in parallel, and combining the results of executing the algorithm on each of the segments to form the output of the serial data processing algorithm. | 01-16-2014 |
20140019694 | PARALLELL PROCESSING OF A SINGLE DATA BUFFER - Technologies for executing a serial data processing algorithm on a single variable-length data buffer includes padding data segments of the buffer, streaming the data segments into a data register and executing the serial data processing algorithm on each of the segments in parallel. | 01-16-2014 |
20140019764 | METHOD FOR SIGNING AND VERIFYING DATA USING MULTIPLE HASH ALGORITHMS AND DIGESTS IN PKCS - Methods, systems, and apparatuses are disclosed for signing and verifying data using multiple hash algorithms and digests in PKCS including, for example, retrieving, at the originating computing device, a message for signing at the originating computing device to yield a signature for the message; identifying multiple hashing algorithms to be supported by the signature; for each of the multiple hashing algorithms identified to be supported by the signature, hashing the message to yield multiple hashes of the message corresponding to the multiple hashing algorithms identified; constructing a single digest having therein each of the multiple hashes of the messages corresponding to the multiple hashing algorithms identified and further specifying the multiple hashing algorithms to be supported by the signature; applying a signing algorithm to the single digest using a private key of the originating computing device to yield the signature for the message; and distributing the message and the signature to receiving computing devices. Other related embodiments are disclosed. | 01-16-2014 |
20140053000 | INSTRUCTIONS TO PERFORM JH CRYPTOGRAPHIC HASHING - A method is described. The method includes executing one or more JH_SBOX_L instruction to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_Permute instruction to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed | 02-20-2014 |
20140082328 | METHOD AND APPARATUS TO PROCESS 4-OPERAND SIMD INTEGER MULTIPLY-ACCUMULATE INSTRUCTION - According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand. | 03-20-2014 |
20140093069 | INSTRUCTION SET FOR MESSAGE SCHEDULING OF SHA256 ALGORITHM - A processor includes a first execution unit to receive and execute a first instruction to process a first part of secure hash algorithm 256 (SHA256) message scheduling operations, the first instruction having a first operand associated with a first storage location to store a first set of message inputs and a second operand associated with a second storage location to store a second set of message inputs. The processor further includes a second execution unit to receive and execute a second instruction to process a second part of the SHA256 message scheduling operations, the second instruction having a third operand associated with a third storage location to store an intermediate result of the first part and a third set of message inputs and a fourth operand associated with a fourth storage location to store a fourth set of message inputs. | 04-03-2014 |
20140095844 | Systems, Apparatuses, and Methods for Performing Rotate and XOR in Response to a Single Instruction - Disclosed herein are systems, apparatuses, and methods performing in a computer processor of performing a rotate and XOR in response to a single XOR and rotate instruction, wherein the rotate and XOR instruction includes a first and second source operand, a destination operand, and an immediate value. | 04-03-2014 |
20140095891 | INSTRUCTION SET FOR SHA1 ROUND PROCESSING ON 128-BIT DATA PATHS - According to one embodiment, a processor includes an instruction decoder to receive a first instruction to process a SHA1 hash algorithm, the first instruction having a first operand, a second operand, and a third operand, the first operand specifying a first storage location storing four SHA states, the second operand specifying a second storage location storing a plurality of SHA1 message inputs in combination with a fifth SHA1 state. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to perform at least four rounds of the SHA1 round operations on the SHA1 states and the message inputs obtained from the first and second operands, using a combinational logic function specified in the third operand. | 04-03-2014 |
20140122839 | APPARATUS AND METHOD OF EXECUTION UNIT FOR CALCULATING MULTIPLE ROUNDS OF A SKEIN HASHING ALGORITHM - An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows. a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections. | 05-01-2014 |
20140164467 | APPARATUS AND METHOD FOR VECTOR INSTRUCTIONS FOR LARGE INTEGER ARITHMETIC - An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register. | 06-12-2014 |
20140177823 | METHODS, SYSTEMS AND APPARATUS TO REDUCE PROCESSOR DEMANDS DURING ENCRYPTION - Methods and apparatus are disclosed to reduce processor demands during encryption. A disclosed example method includes detecting a request for the processor to execute an encryption cipher determining whether the encryption cipher is associated with a byte reflection operation, preventing the byte reflection operation when a buffer associated with the encryption cipher will not cause a carryover condition, and incrementing the buffer via a shift operation before executing the encryption cipher. | 06-26-2014 |
20140185793 | INSTRUCTIONS PROCESSORS, METHODS, AND SYSTEMS TO PROCESS SECURE HASH ALGORITHMS - A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements a | 07-03-2014 |
20140189369 | Instructions Processors, Methods, and Systems to Process Secure Hash Algorithms - A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements a | 07-03-2014 |
20140195782 | METHOD AND APPARATUS TO PROCESS SHA-2 SECURE HASHING ALGORITHM - A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction. | 07-10-2014 |
20140195817 | THREE INPUT OPERAND VECTOR ADD INSTRUCTION THAT DOES NOT RAISE ARITHMETIC FLAGS FOR CRYPTOGRAPHIC APPLICATIONS - A method is described that includes performing the following within an instruction execution pipeline implemented on a semiconductor chip: summing three input vector operands through execution of a single instruction; and, not raising any arithmetic flags even though a result of the summing creates more bits than circuitry designed to transport the summation is able to transport. | 07-10-2014 |
20140205084 | INSTRUCTIONS TO PERFORM JH CRYPTOGRAPHIC HASHING IN A 256 BIT DATA PATH - A method is described. The method includes executing one or more JH_SBOX_L instructions to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_P instructions to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed. | 07-24-2014 |
20140237218 | SIMD INTEGER MULTIPLY-ACCUMULATE INSTRUCTION FOR MULTI-PRECISION ARITHMETIC - A multiply-and-accumulate (MAC) instruction allows efficient execution of unsigned integer multiplications. The MAC instruction indicates a first vector register as a first operand, a second vector register as a second operand, and a third vector register as a destination. The first vector register stores a first factor, and the second vector register stores a partial sum. The MAC instruction is executed to multiply the first factor with an implicit second factor to generate a product, and to add the partial sum to the product to generate a result. The first factor, the implicit second factor and the partial sum have a same data width and the product has twice the data width. The most significant half of the result is stored in the third vector register, and the least significant half of the result is stored in the second vector register. | 08-21-2014 |
20150082047 | EFFICIENT MULTIPLICATION, EXPONENTIATION AND MODULAR REDUCTION IMPLEMENTATIONS - In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment e | 03-19-2015 |
20150089195 | METHOD AND APPARATUS FOR PERFORMING A SHIFT AND EXCLUSIVE OR OPERATION IN A SINGLE INSTRUCTION - Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value. | 03-26-2015 |
20150089196 | METHOD AND APPARATUS FOR PERFORMING A SHIFT AND EXCLUSIVE OR OPERATION IN A SINGLE INSTRUCTION - Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value. | 03-26-2015 |
20150089197 | METHOD AND APPARATUS FOR PERFORMING A SHIFT AND EXCLUSIVE OR OPERATION IN A SINGLE INSTRUCTION - Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value. | 03-26-2015 |
20150089199 | ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION EITHER WITHOUT WRITING OR READING FLAGS - A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag. | 03-26-2015 |
20150089200 | ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION EITHER WITHOUT WRITING OR READING FLAGS - A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag. | 03-26-2015 |
20150089201 | ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION EITHER WITHOUT WRITING OR READING FLAGS - A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag. | 03-26-2015 |
20150098563 | Generating Multiple Secure Hashes from a Single Data Buffer - One embodiment provides an apparatus. The apparatus includes a single instruction multiple data (SIMD) hash module configured to apportion at least a first portion of a message of length L to a number (S) of segments, the message including a plurality of sequences of data elements, each sequence including S data elements, a respective data element in each sequence apportioned to a respective segment, each segment including a number N of blocks of data elements and to hash the S segments in parallel, resulting in S segment digests, the S hash digests based, at least in part, on an initial value and to store the S hash digests; a padding module configured to pad a remainder, the remainder corresponding to a second portion of the message, the second portion related to the length L of the message, the number of segments and a block size; and a non-SIMD hash module configured to hash the padded remainder, resulting in an additional hash digest and to store the additional hash digest. | 04-09-2015 |
20150256195 | APPARATUS AND METHOD TO ACCELERATE COMPRESSION AND DECOMPRESSION OPERATIONS - Methods and apparatuses relating to an instruction to decode encoded information of a compression scheme are described. In one embodiment, a processor includes a decode unit to decode an instruction, and an execution unit to execute the instruction, the execution unit including a state machine and content addressable memory (CAM) circuitry, the state machine to receive a pointer to a stream of encoded information of a compression scheme, fetch a section of the encoded information, and apply the section of the encoded information to the CAM circuitry to obtain decoded information. | 09-10-2015 |
20160085555 | TECHNOLOGIES FOR EFFICIENT LZ77-BASED DATA DECOMPRESSION - Technologies for data decompression include a computing device that reads a symbol tag byte from an input stream. The computing device determines whether the symbol can be decoded using a fast-path routine, and if not, executes a slow-path routine to decompress the symbol. The slow-path routine may include data-dependent branch instructions that may be unpredictable using branch prediction hardware. For the fast-path routine, the computing device determines a next symbol increment value, a literal increment value, a data length, and an offset based on the tag byte, without executing an unpredictable branch instruction. The computing device sets a source pointer to either literal data or reference data as a function of the tag byte, without executing an unpredictable branch instruction. The computing device may set the source pointer using a conditional move instruction. The computing device copies the data and processes remaining symbols. Other embodiments are described and claimed. | 03-24-2016 |