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| 20130077406 | Flash Memory Device - A flash memory device is provided. The flash memory device includes a memory cell array and a pre-charge unit. The pre-charge unit, coupled to a plurality of bit lines corresponding with the memory cell array, pre-charges the bit lines to a predetermined voltage during a pre-charge stage. The pre-charge unit includes a voltage stabilizing unit to provide a constant current to the bit lines. Due to the voltage stabilizing unit, in a programming process, the voltage applied to the bit lines which are not related with programming may not drop as a result of current leakage. Therefore, the memory cells except the memory cell to be programmed are kept in cut off state, without a current passing. As a result, interference with the memory cells which are not to be programmed may be effectively avoided and the accuracy of programming may be improved. | 03-28-2013 |
| 20130235670 | FLASH MEMORY - A flash memory is disclosed. The flash memory includes a flash memory chip; a serial-to-parallel converter for receiving and converting a serial data to a parallel data; and a data mode decision circuit connected to an output terminal of the serial-to-parallel converter for generating an inversion control signal through the parallel data and for applying an inversion processing to the parallel data and then outputting an inverted parallel data to the flash memory chip under the control of the inversion control signal. By converting the serial data to a parallel data and then writing the parallel data into the flash memory chip, a lower proportion of the inversion control signal to the total amount of data is achieved, and therefore less area is consumed while the same programming efficiency and average programming power is maintained compared with a flash memory adopting the bit inversion technique of the prior art. | 09-12-2013 |
| 20140085986 | MEMORY ARRAY DEVICE AND METHOD FOR REDUCING READ CURRENT OF THE SAME - A memory array device is disclosed, which includes a plurality of memory array rows, each memory array row including a plurality of subsidiary memory arrays and a switch arranged between every adjacent two subsidiary memory arrays; wherein each subsidiary memory array includes: a memory unit for storing a data; a programming indication bit arranged prior to the memory unit for indicating whether the subsidiary memory array has been programmed; and an inversion indication bit arranged subsequent to the memory unit for indicating whether a data had been inverted before being written in the memory unit of the subsidiary memory array. A method for reducing a read current of a memory array device is also disclosed. | 03-27-2014 |
| 20140152378 | CHARGE PUMP CIRCUIT - A charge pump circuit includes a charge pump, a regulator circuit, and a load current, wherein the charge pump circuit further includes: a filter circuit connected to an output terminal of the charge pump for filtering an output voltage of the charge pump; and a ripple control circuit connected both to the output terminal of the charge pump and to the filter circuit for reducing the output voltage of the charge pump upon an increase thereof, thereby attenuating ripples contained in the output voltage of the charge pump. The charge pump circuit is capable of enabling a relatively stable output voltage for the charge pump, thus benefiting a downstream integrated circuit. | 06-05-2014 |
| 20140177333 | ROW DECODING CIRCUIT AND MEMORY - A row decoding circuit and a memory are provided. The row decoding circuit is adapted for providing a word line operation voltage and a control-gate line operation voltage to a dual-bit split gate flash memory array, and includes a dummy row decoding unit, at least one row decoding unit and a driving voltage generating circuit. The dummy row decoding unit includes a first dummy control-gate line voltage output, a second dummy control-gate line voltage output and at least one dummy word line voltage output. The row decoding unit includes a first control-gate line voltage output, a second control-gate line voltage output and at least one word line voltage output. The driving voltage generating circuit is adapted for providing a third driving voltage to the first control-gate line voltage output and the second control-gate line voltage output. | 06-26-2014 |
| 20140211575 | Charge Pump Circuit and Memory - Charge pump circuit and memory are provided. The charge pump circuit includes a clock driving unit, a voltage boosting unit, a boosting swing control unit, a first and second NMOS tubes, a first and second current mirror units. The clock driving unit is adapted to form and output clock driving signals to the voltage boosting unit. The voltage boosting unit is adapted to boost voltage and output it to the boosting swing control unit and the first current minor unit. The boosting swing control unit is adapted to output boosting swing control signals to the first NMOS tube. The first current minor unit is to output first mirror current and the second current minor unit is to minor the first mirror current and output second minor current. Frequency of the clock driving signal varies with leakage current load, and size of the charge pump circuit and power consumption are reduced. | 07-31-2014 |
| 20150194193 | MEMORY AND READING METHOD THEREOF, AND CIRCUIT FOR READING MEMORY - Memory and reading method thereof, and circuit for reading memory are provided. The memory includes a memory array; a row decoding circuit configured to apply word line voltage to selected word line in reading operation; a column decoding circuit configured to select a source line connected with a target memory cell based on reading data, the target memory cell using the selected word line; and a reading circuit including first and second input terminals and a comparison node, the first input terminal being connected with the source line of the memory cell through the column decoding circuit and configured to let in reading current of the target memory cell, the second input terminal being configured to let in base current, the comparison node being configured to compare reading current with reference current related to the base current to output reading result. The memory is driven under low voltage. | 07-09-2015 |
| 20150194878 | CHARGE PUMP SYSTEM AND MEMORY - Charge pump system and memory are provided. The system includes: a first enabling control unit, adapted to delay at least one start-up signal of the system to obtain and output an oscillating enabling signal after receiving the at least one start-up signal and a voltage boosting enabling signal; a second enabling control unit, adapted to delay the oscillating enabling signal to obtain and output a charge pump enabling signal after receiving the oscillating enabling signal and the voltage boosting enabling signal; a clock oscillating unit, adapted to generate a clock signal after receiving the oscillating enabling signal; and at least one charge pump cell, adapted to output a boosting voltage after receiving the charge pump enabling signal and the clock signal, obtain the voltage boosting enabling signal based on the boosting voltage, and output the voltage boosting enabling signal. Power consumption of the system in a start-up process is reduced. | 07-09-2015 |
| 20150332776 | FLASH-MEMORY LOW-SPEED READ MODE CONTROL CIRCUIT - The present invention discloses a flash-memory low-speed read mode control circuit, which comprises a charge pump, a first voltage division circuit composed of two resistors and a first switch interconnected in series, and a second voltage division circuit composed of two capacitors interconnected in series. The first switch is used for switching between the data read mode of the low-speed read mode and the charge pump electric-leakage mode. In the data read mode, a first component voltage formed by the two resistors is fed back to the input terminal of the charge pump through a comparator, an NAND gate and a buffer, making a stable value of the output voltage of the charge pump proportional to the first component voltage. In the charge pump electric-leakage mode, the second voltage division circuit monitors the output voltage of the charge pump: when the output voltage is below a low threshold voltage, a feedback signal is formed and sent to the input terminal of the charge pump to make the charge pump turned on; when the output voltage is above a low threshold voltage, a feedback signal is formed and sent to the input terminal of the charge pump to make the charge pump stop working. The present invention can reduce the average current of the entire low-speed read mode significantly, and reduce the power consumption of the read process. | 11-19-2015 |
| Patent application number | Description | Published |
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| 20080298673 | THREE-DIMENSIONAL DATA REGISTRATION METHOD FOR VISION MEASUREMENT IN FLOW STYLE BASED ON DOUBLE-SIDED TARGET - The present disclosure is directed to a three-dimensional data registration method for vision measurement in flow style based on a double-sided target. An embodiment of the disclosed method that comprises A. Setting up two digital cameras which can observe the entire measured object; B. Calibrating intrinsic parameters and a transformation between the two digital camera coordinate frames; C. A double-sided target being placed near the measured area of the measured object, the two digital cameras and a vision sensor taking images of at least three non-collinear feature points of the double-sided target; D. Removing the target, measuring the measured area by using the vision sensor; E. Respectively computing the three dimensional coordinates of the feature points in the global coordinate frame and in the vision sensor coordinate frame; F. Estimating the transformation from the vision sensor coordinate frame to the global coordinate frame through the three dimensional coordinates of the three or more non-collinear feature points obtained at step E, then transforming the three dimensional data of the measured area to the global coordinate frame; and G. Repeating step C, D, E, F, then completing three dimensional data registration for all measured areas. The present disclosure improves three dimensional data registration precision and efficiency. | 12-04-2008 |
| 20080317283 | SIGNAL PROCESSING METHOD AND DEVICE FOR MULTI APERTURE SUN SENSOR - The disclosure relates to a signal processing method for multi aperture sun sensor comprising the following steps: reading the information of sunspots in a row from a centroid coordinate memory, judging the absence of sunspots in that row, identifying the row and column index of the sunspots in the complete row, selecting the corresponding calibration parameter based on the row and column index, calculating attitude with the attitude calculation module the corresponding to identified sunspots, averaging the accumulated attitude of all sunspots and outputting the final attitude. At the same time, a signal processing device for multi aperture sun sensor is also presented. It is comprised of a sunspot absence judgment and an identification module and an attitude calculation module. The disclosure implements the integration of sun sensors without additional image processor or attitude processor, reduces field programmable gate array resource and improves the reliability of sun sensors. | 12-25-2008 |
| 20090012731 | METHOD AND DEVICE FOR CALIBRATION OF DIGITAL SUN SENSOR - A method for calibration of a digital sun sensor is disclosed. The method comprises following steps. First, an integrated mathematic model for imaging of a sun sensor is established according to the external and internal parameters of the calibration system of the sun sensor. Next, the two axis of the rotator are rotated by different angles. Then, calibration points' data are acquired and sent to a processing computer through an interface circuit. Finally, a two-step calibration program is implemented to calculate the calibration parameters by substituting the calibration points' data to the integrated mathematic model. The disclosure also relates to an application device of the calibration method. The device comprises: a sun simulator to provide the incident sunlight, a two-axis rotator to acquire different the calibration points' data, and a processing computer to record the calibration points' data and calculate the calibration parameters. The calibration method and device apply to many kinds of digital sun sensors. By integrated external and internal parameters modeling, the disclosure improves calibration precision. Meanwhile, the whole calibration process is simplified because precise installation and adjustment is not required. | 01-08-2009 |
| 20090012734 | METHOD AND DEVICE FOR CALIBRATION OF DIGITAL CELESTIAL SENSOR - A method for calibration of a digital celestial sensor is disclosed. The method comprises the following steps: firstly, an integrated mathematic model for imaging of a celestial sensor is established according to external and internal parameters of the calibration system of the celestial sensor. Secondly, by rotating two axes of a rotator by different angles, calibration points data are acquired and sent to a processing computer through an interface circuit. Finally, a two-step calibration program is implemented to calculate the calibration parameters by substituting calibration points' data to the integrated mathematic model. The disclosure also relates to an application device of the calibration method, wherein the device comprises: a celestial simulator to provide simulated sunlight or starlight, a two-axis rotator to acquire different the calibration points' data, a processing computer to record the calibration points' data and calculate the calibration parameters. The calibration method and device apply to many kinds of digital celestial sensors. By integrating external and internal parameters modeling, the disclosure improves the calibration precision. Meanwhile, the whole calibration process is simplified because precise installation and adjustment is not required. | 01-08-2009 |
| 20090059011 | CALIBRATION METHOD FOR STRUCTURE PARAMETERS OF STRUCTURED-LIGHT VISION SENSOR - This disclosure provides a calibration method for structure parameters of a structured-light vision sensor, which includes setting up the coordinate frames of a camera, image plane and target for calibration. The calculation of coordinates in the camera coordinate frame of stripes, projected by structured-light, on the planar target and a structured-light equation fitting according to the coordinates in the camera coordinate frame of the stripes on the planar target, by moving the planar target arbitrarily multiple times. The calibration method of the structured-light vision sensor provided by the disclosure is easy to operate and no auxiliary apparatus is needed, which can not only promote the efficiency of the calibration of structured-light, but also extend the application scope of calibration of structured-light. | 03-05-2009 |
| 20090112487 | Vehicle dynamic measurement device and method for comprehensive parameters of rail wear - The invention discloses a vehicle dynamic measurement device for comprehensive parameters of rail wear, which comprises a vision sensor, a computer and a milometer. A high-speed image acquisition card and a measurement module are installed in the computer. The vision sensor comprises imaging system for rail cross-section and a raster projector which can project more than one light plane perpendicular to the measured rail. The measurement module is used for calculating vertical wear, horizontal wear, the amplitude and wavelength of corrugation wear. The invention also discloses a vehicle dynamic measurement method for comprehensive parameters of rail wear. The invention can increase the sampling rate of image sensing and acquisition hardware equipment with no need of improving the performance of it, thereby satisfy high-speed on-line dynamic measurement requirements for corrugation wear, and the amplitude and wavelength of corrugation wear can be calculated more precisely. | 04-30-2009 |
| 20120024575 | THERMAL PAD AND METHOD OF FORMING THE SAME - A thermal pad ( | 02-02-2012 |
| 20120162414 | Global Calibration Method With Apparatus Based on Rigid Bar for Multi-Sensor Vision - The present disclosure provides a global calibration method based on a rigid bar for a multi-sensor vision measurement system, comprising: step 1, executing the following procedure for at least nine times: placing, in front of two vision sensors to be calibrated, a rigid bar fasten with two targets respectively corresponding to the vision sensors; capturing images of the respective targets by their corresponding vision sensors; extracting coordinates of feature points of the respective targets in their corresponding images; and computing 3D coordinates of each feature points of the respective targets under their corresponding vision sensor coordinate frames; and Step 2, computing the transformation matrix between the two vision sensors, with the constraint of the fixed position relationship between the two targets. The present disclosure also provides a global calibration apparatus based on a rigid bar for a multi-sensor vision measurement system. Putting the present disclosure to use can increase the accuracy of the global calibration, and also be suitable for the calibration of the multi-sensor vision system in the extremely large working space, which enlarges the application range of the present disclosure. | 06-28-2012 |
| 20130058581 | Microscopic Vision Measurement Method Based On Adaptive Positioning Of Camera Coordinate Frame - The present disclosure provides a microscopic vision measurement method based on the adaptive positioning of the camera coordinate frame which includes: calibrating parameters of a microscopic stereo vision measurement model ( | 03-07-2013 |
| 20140321735 | Method and computer program product of the simultaneous pose and points-correspondences determination from a planar model - A method and software for the simultaneous pose and points-correspondences determination from a planar model are disclosed. The method includes using a coarse pose estimation algorithm to obtain two possible coarse poses, and using each one of the two coarse poses as the initialization of the extended TsPose algorithm to obtain two candidate estimated poses; selecting one from the two candidate estimated poses based on the cost function value. Thus, The method solves the problem of pose redundancy in the simultaneous pose and points-correspondences determination from a planar model, i.e., the problem that the numbers of estimated poses increase exponentially as the iterations go. The disclosed embodiment is based on the coplanar points, and does not place restriction on the shape of a planar model. It performs well in a cluttered and occluded environment, and is noise-resilient in the presence of different levels of noise. | 10-30-2014 |
