Patent application number | Description | Published |
20140281255 | PAGE STATE DIRECTORY FOR MANAGING UNIFIED VIRTUAL MEMORY - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281256 | FAULT BUFFER FOR RESOLVING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281296 | FAULT BUFFER FOR TRACKING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281357 | COMMON POINTERS IN UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281358 | MIGRATION SCHEME FOR UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
Patent application number | Description | Published |
20080251840 | ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE - An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array. | 10-16-2008 |
20090102538 | ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE - An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array. | 04-23-2009 |
20100284214 | ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE - An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array. | 11-11-2010 |
20120140571 | ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE - An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array. | 06-07-2012 |
Patent application number | Description | Published |
20090243684 | METHOD AND DEVICE FOR GENERATING A DIGITAL DATA SIGNAL AND USE THEREOF - In an embodiment, the present invention relates to an integrated circuit comprising at least one data signal input (data | 10-01-2009 |
20150092592 | ENABLING ENCAPSULATION IN NETWORKS - Embodiments generally relate to enabling encapsulation in networks. In one embodiment, a method includes receiving a message from an edge configuration device, wherein the message contains shortest path bridging (SPB) configuration information. The method also includes performing provider backbone bridge (MAC-in-MAC) encapsulation in response to receiving the message. | 04-02-2015 |
20150095449 | MESSAGE TRANSMISSION IN NETWORKS - Embodiments generally relate to message transmission in networks. In one embodiment, a method includes enabling a user to provide shortest path bridging (SPB) configuration information. The method also includes receiving the SPB configuration information from the user. The method also includes sending the SPB configuration information to an edge server device. | 04-02-2015 |
20150095467 | ENABLING CONFIGURATION IN NETWORKS - Embodiments generally relate to enabling configuration in networks. In one embodiment, a method includes receiving a message from an edge configuration device, wherein the message contains shortest path bridging (SPB) configuration information. The method also includes performing an intermediate system-to-intermediate system (IS-IS) configuration in response to receiving the message. | 04-02-2015 |
Patent application number | Description | Published |
20150023398 | VOLTAGE REGULATOR FOR A SERIALIZER/DESERIALIZER COMMUNICATION APPLICATION - The voltage regulator device has a wide band amplifier having an input reference voltage, Vref and an input feedback voltage, Vfbk. The device has a source follower coupled to the wide band amplifier, the source follower coupled to an output of the wide band amplifier. The device has a VDD source, a regulator output, and a current source coupled to the source follower and the VDD source. The device has a low frequency path comprising a first transistor. The first transistor has a first gate, a first source, and a first drain. The first source is coupled to the VDD source. The first gate is coupled to a slow node, and the first drain is coupled to the regulator output. The low frequency path comprises a RC network, which has a capacitor, a resistor, and the slow node configured between the resistor and the capacitor. The device has a high frequency path comprising a second transistor. The second transistor has a second gate, a second source, and a second drain. The second source is coupled to the VDD source. The second gate is coupled to a fast node, and the second drain is coupled to the regulator output. | 01-22-2015 |
20150280902 | CMOS INTERPOLATOR FOR A SERIALIZER/DESERIALIZER COMMUNICATION APPLICATION - A phase interpolator (PI) is provided to adjust the phase of a clock such that the phase is aligned to an incoming data pattern from a data stream. The data can be captured from a device such as a flip-flop or the like. The present technique uses a PI (digital to phase) and a digital state machine in a feedback loop to set the correct digital code to the PI inputs to achieve an appropriate clock phase. Of course, there can be variations. | 10-01-2015 |
20160103023 | VOLTAGE AND TEMPERATURE SENSOR FOR A SERIALIZER/DESERIALIZER COMMUNICATION APPLICATION - The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for sensing a voltage and/or temperature from an integrated circuit device such as a Serializer/Deserializer (SerDes) integrated circuit device. But it will be recognized that the technique can be used for monitoring other system on chip devices, such as micro-controllers, digital signal processors, microprocessors, networking devices, application specific integrated circuits, and other integrated circuit devices that may desire on-chip temperature and/or voltage sensing capability. | 04-14-2016 |
Patent application number | Description | Published |
20110075676 | METHOD AND SYSTEM FOR MANAGING MULTIMEDIA MESSAGES USING A MESSAGE INTERMEDIATION MODULE - A system and method for managing multimedia messaging is described. A system includes a messaging intermediation module having, a sender-side interface configured to communicate a multimedia message between the messaging intermediation module and a data gateway of a multimedia messaging system, a recipient-side interface configured to communicate the multimedia message between the messaging intermediation module, an Internet gateway, a message store and forward (MSF) server, and another messaging intermediation module, a message storage module configured to store the multimedia message for forwarding to the Internet gateway, the MSF server, and the other messaging intermediation module, and a workflow engine configured to process the multimedia message. In response to the processing, the workflow engine forwards the multimedia message to the Internet gateway, forwards the multimedia message to the MSF server, or forwards the multimedia message to the other messaging intermediation module. Other embodiments are also described. | 03-31-2011 |
20110082924 | MANAGING NETWORK TRAFFIC BY EDITING A MANIFEST FILE - A technique for controlling the streaming of content through a network is disclosed. In an embodiment, the technique involves editing the manifest file that is used to implement an HTTP adaptive bit rate streaming protocol. For example, a manifest file is received at an intermediate network device in response to a request from a client for a content element, the manifest file is then edited at the intermediate network device, and then the edited manifest file is sent to the client. In an embodiment, editing the manifest file involves deleting and/or inserting a URI within the manifest file. | 04-07-2011 |
20110082946 | MANAGING NETWORK TRAFFIC USING INTERMEDIATE FLOW CONTROL - A technique for controlling the streaming of content through a network is disclosed. The technique involves changing the rate at which content chunks are sent from an intermediate network device in order to cause a client to request content chunks that are encoded at a different bit rate. For example, an intermediate network device can reduce the rate at which content chunks are sent to a client in order to cause the client to adapt to the reduced flow rate by requesting content chunks that are encoded at a lower bit rate. Causing a client to request content chunks that are encoded at a lower bit rate can reduce the bandwidth demand in a wireless communications network. | 04-07-2011 |
20110093264 | Providing Information Services Related to Multimodal Inputs - A system and method provides information services related to multimodal inputs. Several different types of data used as multimodal inputs are described. Also described are various methods involving the generation of contexts using multimodal inputs, synthesizing context-information service mappings and identifying and providing information services. | 04-21-2011 |
20110203006 | METHOD AND SYSTEM FOR DELIVERING CLOSED-AUDIENCE CONTENT TO A CLOSED MOBILE AUDIENCE - A method and system for delivering closed-audience content to a closed mobile audience is described. In one embodiment, a method for delivering closed-audience content to a closed mobile audience is described. The method for delivering closed-audience content to a closed mobile audience involves obtaining closed-audience content, establishing a closed mobile audience, identifying a mobile user or a mobile device as being part of the closed mobile audience, and delivering the closed-audience content to the mobile user or the mobile device. Other embodiments are also described. | 08-18-2011 |
20130057583 | PROVIDING INFORMATION SERVICES RELATED TO MULTIMODAL INPUTS - A system and method provides information services related to multimodal inputs. Several different types of data used as multimodal inputs are described. Also described are various methods involving the generation of contexts using multimodal inputs, synthesizing context-information service mappings and identifying and providing information services. | 03-07-2013 |
Patent application number | Description | Published |
20130138911 | MEMORY CONTROLLER WITH RECONFIGURABLE HARDWARE - Memory controller concepts are disclosed in which hardware resources of a memory controller can be re-used or re-configured to accommodate various different memory configurations. The memory configuration may be stored in mode register bits ( | 05-30-2013 |
20130339775 | POWER-MANAGEMENT FOR INTEGRATED CIRCUITS - An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path. | 12-19-2013 |
20140029331 | MEMORY DEVICE WITH MULTI-MODE DESERIALIZER - An integrated circuit memory device is disclosed. The memory device includes a memory core having a timing input to receive a clock signal. An interface couples to the memory core. The interface includes a receiver to receive a serial stream of write data bits and a sampler clocked by a strobe signal to generate serialized write data. The interface also includes a deserializer and control logic. The deserializer includes an input to receive the serialized write data and an output to generate parallel data responsive to a control signal generated by the control logic. In a first mode of operation, the control logic generates the control signal with respect to the clock signal. In a second mode of operation, the control logic generates the control signal with respect to the strobe signal. | 01-30-2014 |
20140052934 | Memory with Alternative Command Interfaces - A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose. | 02-20-2014 |
20140082234 | COMMUNICATION VIA A MEMORY INTERFACE - A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer. | 03-20-2014 |
20140149618 | CALIBRATION PROTOCOL FOR COMMAND AND ADDRESS BUS VOLTAGE REFERENCE IN LOW-SWING SINGLE-ENDED SIGNALING - A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode. | 05-29-2014 |
20150162061 | MULTI-CYCLE WRITE LEVELING - A memory controller includes logic to determine corresponding reference voltage values and delay values for one or more memory devices. The memory controller includes a command-address (CA) interface to send a command to a memory device to set a reference voltage value of the memory device to a test value, a data interface to write a data pattern to the memory device and read the data pattern from the memory device, and test reference voltage logic to perform a density check on at least a portion of the data pattern read from the memory device and determine whether the test value is a potential reference voltage value based on the density check. An operational reference voltage value selected from one or more potential reference voltage values may be used to determine a delay value. | 06-11-2015 |
20150324309 | COMMUNICATION VIA A MEMORY INTERFACE - A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer. | 11-12-2015 |
20150348612 | POWER-MANAGEMENT FOR INTEGRATED CIRCUITS - An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path. | 12-03-2015 |
Patent application number | Description | Published |
20130304799 | ACCESSING OPEN DATA USING BUSINESS INTELLIGENCE TOOLS - A method for querying an Open Data Protocol (“opendata”) opendata provider includes receiving a relational database query, parsing the relational database query, creating an execution plan, transmitting an opendata query to the opendata provider, transforming a response into a relational format, and providing the transformed response in reply to the relational database query. The method further includes mapping content of an opendata entity data model to a relational model catalog, and processing a portion of the execution plan by an opendata driver implemented at the server. The method can further include the server retrieving document metadata from the opendata provider, building an internal model of the document metadata, and responding to a metadata request. A system for implementing the method and a non-transitory computer readable medium are also disclosed. | 11-14-2013 |
20150310083 | MAPPING NON-RELATIONAL DATABASE OBJECTS INTO A RELATIONAL DATABASE MODEL - According to some embodiments, information may be received about a non-relational database object, such as an InfoSet, InfoSet query, or Advanced Business Application Programming (“ABAP”) function for an enterprise resource planning system. The non-relational database object may then be mapped into a relational database model, such as a model associated with a business intelligence platform. As a result, Structured Query Language (“SQL”) inputs from a business intelligence platform may be used create reports based on information in an enterprise resource planning system. | 10-29-2015 |
Patent application number | Description | Published |
20110180983 | LIFE ENHANCEMENT OF RING ASSEMBLY IN SEMICONDUCTOR MANUFACTURING CHAMBERS - The present invention generally relates to a ring assembly that may be used in an etching or other plasma processing chamber. The ring assembly generally includes an inner ring and an outer ring disposed radially outward of the inner ring. The inner ring will correspond to the location where the majority of erosion occurs during use. This inner ring can be flipped and reused until both sides have eroded beyond their service life. Collectively, the two rings generally have the shape of a single piece ring, but the service life of the ring assembly is longer than a conventional single piece ring. | 07-28-2011 |
20120154974 | HIGH EFFICIENCY ELECTROSTATIC CHUCK ASSEMBLY FOR SEMICONDUCTOR WAFER PROCESSING - The present invention generally provides a high efficiency electrostatic chuck including a flex stack having an electrode disposed between two layers of dielectric material. At least one of the layers is a standard or high purity thermoplastic film. The flex stack may have a matte finish on the substrate supporting surface to provide benefits such as improved temperature distribution across the surface of the chuck. The non-substrate supporting or pedestal receiving side of the flex stack may be plasma treated to provide a desired surface finish, which is then bonded to a pedestal using an acrylic or epoxy adhesive resulting in superior bonding strength compared to traditional polymer electrostatic chucks. The electrode may be a sheet electrode on a release liner, which enables ease of manufacturing. | 06-21-2012 |
20130035022 | Two-Part Plastic Retaining Ring - A retaining ring includes a generally annular lower portion and a generally annular upper portion. The lower portion has a bottom surface for contacting a polishing pad during polishing and a top surface. The upper portion has a bottom surface secured to the top surface of the lower portion and a top surface configured to be mechanically affixed to and abut a rigid base of a carrier head. The lower portion is a first plastic, and the upper portion is a different second plastic that is about the same or more rigid than the first plastic. | 02-07-2013 |
20130324017 | TWO-PART RETAINING RING WITH INTERLOCK FEATURES - A retaining ring includes an annular lower portion and an annular upper portion. The annular lower portion has a main body with a bottom surface for contacting a polishing pad during polishing, an inner rim projecting upward from the main body, an outer rim projecting upward from the main body and separated from the inner rim by a gap, and a plurality of azimuthally separated interlock features positioned between the inner rim and the outer rim, each interlock feature projecting upwardly from the main body. The annular upper portion has a top surface and a bottom surface and a plurality of azimuthally separated recesses in the bottom surface, the recesses defining thin portions of the upper portion, the plurality of interlock features fitting into the plurality of recesses. The lower portion is a plastic and the upper portion is a material that is more rigid than the plastic. | 12-05-2013 |
20140167327 | SURFACE ANNEALING OF COMPONENTS FOR SUBSTRATE PROCESSING CHAMBERS - A method of fabricating a processing chamber component comprises forming a processing chamber component having a structural body with surface regions having microcracks, and directing a laser beam onto the microcracks of the surface regions of the structural body for a sufficient time to heal and close off the microcracks by themselves. | 06-19-2014 |
20140238604 | LIFE ENHANCEMENT OF RING ASSEMBLY IN SEMICONDUCTOR MANUFACTURING CHAMBERS - The present invention generally relates to a ring assembly that may be used in an etching or other plasma processing chamber. The ring assembly generally includes an inner ring body having a top planar surface and a bottom planar surface, and an outer ring body having a top surface, a bottom surface substantially parallel to the top surface, and an inside surface that extends between the top surface and the bottom surface, the inside surface having a roof covering a portion of the inner ring body when the inner ring body is disposed adjacent the roof, wherein the inner ring body can be flipped into a different position so that a portion of the inner ring body that is not covered by the roof provides a substantially planar surface. | 08-28-2014 |
20140287662 | RETAINING RING WITH ATTACHABLE SEGMENTS - A retaining ring includes a generally annular upper portion having a top surface configured to be connected to a base of a carrier head and a lower surface, and a plurality of substantially identical arcuate segments detachably secured to the upper portion to form an annular lower portion. Each of the arcuate segments has an upper surface that abuts the lower surface of the upper portion and a bottom surface for contacting a polishing pad during polishing. | 09-25-2014 |
Patent application number | Description | Published |
20100192136 | OPTIMIZED JAVASERVER PAGES LIFECYCLE MODEL - Systems and methods are provided that service a JavaServer Page (“JSP”), including receiving a request for a JSP page, parsing source code for the JSP page, creating a tree of the parsed source code. executing the tree in memory, and returning the requested JSP page. Accordingly, JSP pages do not require repeated recompilation, and JSP pages with customized content may be quickly regenerated with a low performance overhead. | 07-29-2010 |
20150370549 | SYSTEM AND METHOD FOR SUPPORTING DEPLOYMENT IN A MULTITENANT APPLICATION SERVER ENVIRONMENT - In accordance with an embodiment, described herein is a system and method for supporting deployment in an application server environment. A resource, for example an application or library, can be deployed to different resource groups in different partitions in a domain, to a resource group template referenced by the different resource groups, or to a domain-level resource group. One or more additional deployment operations can be performed on a deployed resource by a partition administrator or a system administrator. A deployment API can be provided to enable a plurality to deployment clients to perform the deployment operations, and can be used to derive partition information and target information for the deployment operations when the information is not provided by a partition administrator. Different deployment scopes are defined to allow a same resource to be deployed in different partitions of a domain and outside any partition in the domain. | 12-24-2015 |
Patent application number | Description | Published |
20140106753 | DYNAMIC CARRIER SWITCHING - A rule server detects a condition pertaining to a switch of a user device to a preferred wireless carrier, and sends a message to the user device indicating a switch to the preferred wireless carrier. | 04-17-2014 |
20140329552 | DUTY CYCLING TO REDUCE AVERAGE TRANSMIT POWER - A user device receives a command to transmit information at a transmit power level specified by a wireless carrier. The user device determines whether transmitting the information at the specified transmit power level using a first duty cycle will cause the user device to violate a condition. Responsive to determining that transmitting the information at the specified transmit power level using the first duty cycle will cause the user device to violate the condition, the user device determines a new duty cycle that is lower than the first duty cycle, and transmits the information using the new duty cycle. | 11-06-2014 |
20140350710 | Tote Based Item Tracking - This disclosure describes a system for managing inventory as it transitions into a materials handling facility, as it transitions between locations within a materials handling facility and/or as it transitions out of a materials handling facility. In some instances, a user (e.g., picker or picking agent) may retrieve an item from an inventory location and place the item into a tote. The systems described herein detect the item when it is added to or removed from the tote. | 11-27-2014 |
20140350711 | Inventory Tracking - This disclosure describes a system for managing inventory as it transitions into a materials handling facility, as it transitions between locations within a materials handling facility and/or as it transitions out of a materials handling facility. In some instances, a user (e.g., picker or picking agent) may retrieve an item from an inventory location and place the item into a tote. The systems described herein detect the item when it is added to or removed from the tote. | 11-27-2014 |
20140350715 | Inventory Transitions - This disclosure describes a system for managing inventory as it transitions into a materials handling facility, as it transitions between locations within a materials handling facility and/or as it transitions out of a materials handling facility. In some instances, a user (e.g., picker or picking agent) may retrieve an item from an inventory location and place the item into a tote. The systems described herein detect the item when it is added to or removed from the tote. | 11-27-2014 |
20140351077 | DEVICE CUSTOMIZATION DURING ORDER FULFILLMENT UTILIZING AN EMBEDDED ELECTRONIC TAG - A method for customizing a device during order fulfillment is described. A processing device receives an order for an electronic device, the order comprising customization information that is stored in a memory. The processing device wirelessly transmits the customization information into an electronic tag embedded in the electronic device while the electronic device is enclosed in associated packaging. | 11-27-2014 |
20150099558 | USING SENSORS TO TRIGGER TRANSMIT POWER MANAGEMENT - A user device transmits data at a first transmit power level. The user device detects a presence of a human body part within a predetermined distance from an antenna of the user device using one or more sensors disposed at a back side of the user device. In response to the detection of the presence of the human body part, the user device transmits information at a second transmit power level that is less than the first transmit power level. | 04-09-2015 |