Patent application number | Description | Published |
20110264721 | SIGNAL PROCESSING BLOCK FOR A RECEIVER IN WIRELESS COMMUNICATION - A QRD processor for computing input signals in a receiver for wireless communication relies upon a combination of multi-dimensional Givens Rotations, Householder Reflections and conventional two-dimensional (2D) Givens Rotations, for computing the QRD of matrices. The proposed technique integrates the benefits of multi-dimensional annihilation capability of Householder reflections plus the low-complexity nature of the conventional 2D Givens rotations. Such integration increases throughput and reduces the hardware complexity, by first decreasing the number of rotation operations required and then by enabling their parallel execution. A pipelined architecture is presented ( | 10-27-2011 |
20120134451 | Method and System for a Low-Complexity Soft-Output MIMO Detection - An approach for Soft-output K-Best MIMO detection comprises computing an estimated symbol vector and Log-Likelihood Ratio (LLR) values for transmitted bits. The approach includes a relevant discarded paths selection process, a last-stage on-demand expansion process, and a relaxed LLR computation process. The relevant discarded paths selection process includes analyzing the K-Best paths and discarded paths at each intermediate tree level and selecting only those discarded paths for further processing that will help in LLR computation for at least one of the transmitted bits. The last-stage on-demand expansion process includes expanding K paths at the tree level 2N | 05-31-2012 |
20120294094 | METHOD AND APPARATUS FOR MEMORY FAULT TOLERANCE - A plurality of data lines and a plurality of bit lines may be used to write to and/or read from an array of memory cells. A switching element may select among different mappings between the plurality of data lines and the plurality of bit lines. The array may, for example, consist of N memory cells, the plurality of bit lines may consist of N bit lines, and the plurality of data lines may consist of N data lines, where N is an integer greater than 1. For a write operation in which a data block is to be written to the array, a configuration of the switching element may be controlled based, at least in part, on how sensitive the data block is to a faulty memory cell among the array of memory cells. | 11-22-2012 |
20120294100 | METHOD AND APPARATUS FOR MEMORY POWER AND/OR AREA REDUCTION - A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage V | 11-22-2012 |
20130141995 | METHOD AND APPARATUS FOR MEMORY FAULT TOLERANCE - One or more circuits may include an array of memory cells corresponding to a particular memory address. The one or more circuits may be operable to discover a location of a faulty memory cell in the array of memory cells. The one or more circuits may be operable to arrange the order in which the bits of a data block are stored to said array of memory cells based, at least in part, on said discovered location of said faulty memory cell. | 06-06-2013 |
20130141996 | METHOD AND APPARATUS FOR MEMORY FAULT TOLERANCE - One or more circuits may comprise an array of memory cells corresponding to a particular memory address, and a memory fault mitigation module. The one or more circuits may be operable to write a data block to the array of memory cells. The write operation may comprises a swap of a first portion of the data block with a second portion of the data block in response to a detection that one or more memory cells of the array is faulty, and storing the data block to the array of memory cells after the swap. | 06-06-2013 |
20140141408 | INTEGRATED SENSOR FOR THE RAPID IDENTIFICATION OF BACTERIA USING ISFETS - Disclosed are methods and systems for the detection of bacteria in a sample. The methods comprises contacting the sample with an antibacterial agent and a bacteria identification sensor, and involves the permeabilization of the bacteria by the antibacterial agent, and the subsequent detection of an efflux of potassium ions using a bacteria identification sensor comprising a potassium-sensitive ISFET. Also disclosed are bacteria identification sensor comprising a potassium-sensitive ISFET useful in the practice of the disclosed methods. | 05-22-2014 |
20140191585 | METHOD AND SYSTEM FOR MAXIMUM ACHIEVABLE EFFICIENCY IN NEAR-FIELD COUPLED WIRELESS POWER TRANSFER SYSTEMS - Methods and systems for maximum efficiency achievable in near-field coupled wireless power transfer systems are disclosed and may include configuring coil geometry, independently of load impedance and source impedance, for a transmit (Tx) coil and a receive (Rx) coil based on a media expected to be between the coils during operation. A desired susceptance and conductance may be determined and an impedance of an amplifier for the Tx coil may be configured based on the determined susceptance and conductance. A load impedance for the Rx coil may be configured based on the determined susceptance and conductance. A matching network may be coupled to the amplifier. The Rx coil may be integrated on a complementary metal-oxide semiconductor (CMOS) chip. One or more matching networks may be integrated on the CMOS chip for the configuring of the load impedance for the Rx coil. | 07-10-2014 |
20150016557 | METHOD AND SYSTEM FOR A LOW-COMPLEXITY SOFT-OUTPUT MIMO DETECTION - An approach for Soft-output K-Best MIMO detection comprises computing an estimated symbol vector and Log-Likelihood Ratio (LLR) values for transmitted bits. The approach includes a relevant discarded paths selection process, a last-stage on-demand expansion process, and a relaxed LLR computation process. The relevant discarded paths selection process includes analyzing the K-Best paths and discarded paths at each intermediate tree level and selecting only those discarded paths for further processing that will help in LLR computation for at least one of the transmitted bits. The last-stage on-demand expansion process includes expanding K paths at the tree level 2N | 01-15-2015 |
20150023122 | METHOD AND APPARATUS FOR MEMORY POWER AND/OR AREA REDUCTION - A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage V | 01-22-2015 |
20150076920 | Method And System For A Complementary Metal Oxide Semiconductor Wireless Power Receiver - Methods and systems for a complementary metal oxide semiconductor wireless power receiver may include a receiver chip with an inductor, a configurable capacitance, and a rectifier. The method may include receiving an RF signal utilizing the inductor, extracting a clock signal from the received RF signal, generating a DC voltage utilizing a rectifier circuit, sampling the DC voltage, and adjusting the configurable capacitance based on the sampled DC voltage. The rectifier circuit may include CMOS transistors and T-gate switches for coupling to the inductor. The T-gate switches may be controlled by the generated DC voltage. A signed based gradient-descent algorithm may be utilized to maximize the DC voltage. The DC voltage may be sampled utilizing a comparator powered by the DC voltage, which may adaptively configure the capacitance. The inductor may be shielded utilizing a floating shield. The DC voltage may be increased utilizing a voltage-boosting rectifier. | 03-19-2015 |