Patent application number | Description | Published |
20140164857 | Testing Disk Drives Shared by Multiple Processors in a Supercomputer Complex - According to one embodiment of the present disclosure, an approach is provided in which an interface node selects a logical block address that corresponds to a contiguous memory location located on a storage device that is accessible by multiple interface nodes. The interface node retrieves a logical block address status indicator from a shared memory area and determines, based upon the logical block status indicator, whether the logical block address is utilized by a different interface node. If the logical block address is not utilized by a different interface node, the interface node tests the corresponding contiguous memory location. | 06-12-2014 |
20140297234 | Forecasting production output of computing system fabrication test using dynamic predictive model - A dynamic predictive model of a computing system fabrication test is constructed. The computing system fabrication test is conducted over test sectors. Each test sector corresponds to a different type of the computing system fabrication test, and includes test operations that are individually performed to effectuate the test sector. The dynamic predictive model generates a predicted completion time of each test operation of each test sector. Production output of the computing system fabrication test is forecast for a scenario corresponding to a particular computing system to undergo fabrication testing, by applying the dynamic predictive model to the scenario. The production output is forecast in that a total time remaining until the particular computing system to which the scenario corresponds has completed the fabrication testing is predicted. | 10-02-2014 |
20140297351 | Computing system predictive build - Features to include within a predictive build of a computing system are selected. The predictive build is an anticipated final build of the computing system prior to receiving a firm customer order for the computing system in accordance with which an actual final build of the computing system is then built. A marginal cost of first building the predictive build and then modifying the predictive build to realize the actual final build, as compared to building the actual final build without first building the predictive build and then modifying predictive build to realize the actual final build, is estimated based on the features selected. Responsive to determining that the marginal cost is less than a predetermined acceptable marginal cost limit, the predictive build is built prior to receiving the firm customer order, and then is modified to realize the actual final build upon receiving the firm customer order. | 10-02-2014 |
20140297452 | Computing system predictive build - Features to include within a predictive build of a computing system are selected. The predictive build is an anticipated final build of the computing system prior to receiving a firm customer order for the computing system in accordance with which an actual final build of the computing system is then built. A marginal cost of first building the predictive build and then modifying the predictive build to realize the actual final build, as compared to building the actual final build without first building the predictive build and then modifying predictive build to realize the actual final build, is estimated based on the features selected. Responsive to determining that the marginal cost is less than a predetermined acceptable marginal cost limit, the predictive build is built prior to receiving the firm customer order, and then is modified to realize the actual final build upon receiving the firm customer order. | 10-02-2014 |
20140364984 | Replacement of suspect or marginally defective computing system components during fulfillment test of build-to-order test phase - A fulfillment test of a computing system having components is performed within a build-to-order test phase. Responsive to the fulfillment test failing, the component that most contributed to the fulfillment test failing is replaced, regardless of whether the given component was determined to be suspect or marginally defective pursuant to a fabrication test previously performed within a build-to-plan test phase. Any other component of that contributed to the fulfillment test failing and that was determined to be suspect or marginally defective pursuant to the fabrication test previously performed within the build-to-plan test phase is also replaced. | 12-11-2014 |
20140372066 | VARYING POWER LOAD CONDITIONS ON SYSTEMS UNDER TEST - An apparatus includes a system test module that initiates a system power test for a computer system. The computer system includes one or more power supplies that provide power to system components. The system power test includes determining power system characteristics under various loading conditions. The apparatus includes a configure module that configures a system component during the system power test. The system component uses a higher amount of power after being configured than in a previous un-configured condition. The apparatus includes a de-configure module that de-configures the system component during the system power test. The system component uses a lower amount of power after being de-configured than in a previous configured condition. The apparatus includes a diagnostic module that measures power system performance of the computer system during varying loading conditions caused by configuring and de-configuring one or more system components by the configure module and the de-configure module. | 12-18-2014 |
20150149846 | TESTING A PROCESSOR ASSEMBLY - A testing backplane apparatus includes first test ports configured to receive a first processor assembly under test and the plurality of first test ports may be an even number of first test ports or an odd number of first test ports. The testing backplane apparatus includes second test ports, where each first test port corresponds to a second test port and the second test ports connect to a second processor assembly. The testing backplane apparatus includes a signal pathway from each first test port to a second test port. The signal pathway includes a signal path length within a range between a maximum signal path length and a minimum signal path length. Each port on the first processor assembly corresponds to each port on the second processor assembly and the testing backplane apparatus is configured differently from a backplane used as a final destination for operating the first processor assembly. | 05-28-2015 |