Patent application number | Description | Published |
20100196333 | Device and Process for Producing Fiber Products and Fiber Products Produced Thereby - The present invention is directed to a fiber, preferably bone fiber, having a textured surface, which acts as an effective binding substrate for bone-forming cells and for the induction or promotion of new bone growth by bone-forming cells, which bind to the fiber. Methods of using the bone fibers to induce or promote new bone growth and bone material compositions comprising the bone fibers are also described. The invention further relates to a substrate cutter device and cutter, which are effective in producing substrate fibers, such as bone fibers. | 08-05-2010 |
20110027871 | Apparatus for Demineralizing Osteoinductive Bone - The invention is directed to an apparatus for producing demineralized osteoinductive bone. The apparatus demineralizes bone by subjecting bone, including, for example, ground bone, bone cubes, chips, strips, or essentially intact bone, to either a rapid high volume pulsatile acidification wave process or to a rapid continuous acid demineralization process. The pulsatile acidification wave process includes subjecting bone to two or more rapid pulse/drain cycles in which one or more demineralizing acids is rapidly pulsed into a vessel containing bone, and after a desired period of time, is rapidly drained from the vessel. The continuous acid demineralization process includes subjecting bone to a continuous exchange of demineralizing acid solution in which the demineralizing acid solution is recirculated from the container holding the bone through an ion exchange media. Calcium and phosphate are thereby removed from the bone to produce a regenerated acid, and the regenerated acid is returned to the container holding the bone. Both processes allow bone to be rapidly demineralized to a precise and specific desired residual calcium level without sacrificing osteoinductivity. | 02-03-2011 |
20130316012 | Method of Demineralizing Bone - The invention is directed to an apparatus for producing demineralized osteoinductive bone. The apparatus demineralizes bone by subjecting bone, including, for example, ground bone, bone cubes, chips, strips, or essentially intact bone, to either a rapid high volume pulsatile acidification wave process or to a rapid continuous acid demineralization process. The pulsatile acidification wave process includes subjecting bone to two or more rapid pulse/drain cycles in which one or more demineralizing acids is rapidly pulsed into a vessel containing bone, and after a desired period of time, is rapidly drained from the vessel. The continuous acid demineralization process includes subjecting bone to a continuous exchange of demineralizing acid solution in which the demineralizing acid solution is recirculated from the container holding the bone through an ion exchange media. Calcium and phosphate are thereby removed from the bone to produce a regenerated acid, and the regenerated acid is returned to the container holding the bone. Both processes allow bone to be rapidly demineralized to a precise and specific desired residual calcium level without sacrificing osteoinductivity. | 11-28-2013 |
Patent application number | Description | Published |
20090090097 | Method and apparatus for detecting a non-operational status of a catalyst in an engine exhaust conduit - A quantity of unburned fuel is provided through a combustion chamber of an engine and an exhaust conduit to a catalytic converter. The catalyst in the converter is determined to be non-operational if a post-catalyst temperature sensor does not indicate a sufficient temperature increase between readings before and after provision of the unburned fuel to the combustion chamber. The unburned fuel may be provided by withholding spark ignition to create a misfire in the combustion chamber or, particularly in a direct injection engine, by injecting the fuel during the exhaust stroke. | 04-09-2009 |
20120191275 | SYSTEM AND METHOD FOR OPERATING A VEHICLE CRUISE CONTROL SYSTEM - A control system for a vehicle that includes an engine includes a speed generation module, an airflow determination module, and a throttle control module. The speed generation module generates a desired engine speed during a period after a measured vehicle speed is greater than or equal to a desired vehicle speed, wherein the desired engine speed is based on a difference between the desired vehicle speed and the measured vehicle speed. The airflow determination module determines a desired airflow based on a difference between the desired engine speed and a measured engine speed. The throttle control module determines a desired throttle position based on the desired airflow, and commands a throttle of the engine to the desired throttle position. | 07-26-2012 |
20120191276 | WATERCRAFT THROTTLE CONTROL SYSTEMS AND METHODS - A system for a watercraft includes memory, a communications module, and a throttle control module. The memory includes a first mapping of measured accelerator position to desired throttle opening. The communications module selectively downloads a second mapping of the measured accelerator position to the desired throttle opening to the memory. The throttle control module generates the desired throttle opening based on the measured accelerator position and a selected one of the first and second mappings. A throttle actuator module opens a throttle valve based on the desired throttle opening. | 07-26-2012 |
20120191277 | ENGINE CONTROL SYSTEM AND METHOD FOR A MARINE VESSEL - A system according to the principles of the present disclosure includes a profile storage module, a profile playback module, and a speed control module. The profile storage module stores an acceleration profile specifying a manner of accelerating a marine vessel. The profile playback module, in response to a play command received from a vessel operator, retrieves the acceleration profile and adjusts a desired engine speed based on the acceleration profile. The speed control module controls an engine speed of the marine vessel based on the desired engine speed. | 07-26-2012 |
Patent application number | Description | Published |
20100323929 | Methods for Treating a Well with a Cross-Linked Water-Soluble Polymer-Complexed Metal Cation Network and an Aromatic Compound Capable of Forming a Chelating Agent to Uncross-Link the Polymer - Methods are provided for treating a portion of a well. The method according to this aspect comprises the steps of: (A) forming a treatment fluid, the treatment fluid comprising: (i) water; (ii) a water-soluble polymer; (iii) a complexed metal cation that: (a) has a valence state of at least three; and (b) is capable of cross-linking the water-soluble polymer; and (iv) an aromatic compound that is capable of dissolving, melting, or chemically decomposing, dissociating, or reacting, to form a chelating agent, wherein the chelating agent comprising vicinal substituents containing donor heteroatoms, and wherein the chelating agent is capable of chelating the metal cation; and (B) introducing the treatment fluid into the well. | 12-23-2010 |
20110015101 | STABILIZATION OF EMULSIONS CONTAINING RESINOUS MATERIAL FOR USE IN THE FIELD OF OIL OR GAS WELL TREATMENTS - According to one aspect of the inventions, emulsion compositions are provided. Emulsions according to this aspect include: (a) a water-insoluble resinous material; (b) water; and (c) an emulsifier, wherein the emulsifier comprises a non-ionic, a cationic, or a zwitterionic emulsifier; wherein the continuous phase of the emulsion comprises the water; wherein a dispersed phase of the emulsion comprises the resinous material; wherein the dispersed phase is in the form of droplets having a size distribution range such that at least 50% of the droplets have a size of 0.5 micrometers-500 micrometers; wherein the resinous material of the droplets is in a concentration of at least 5% by weight of the water; and wherein the composition of the droplets has a viscosity of less than 2,000 Poise measured at 20° F. According to another aspect of the inventions, methods are provided for treating a portion of a subterranean formation. Methods according to this aspect include the steps of: (a) forming an emulsion according to the composition described above; and (b) introducing the emulsion into a portion of a subterranean formation. | 01-20-2011 |
20110071056 | Degradable Surfactants, Including Degradable Gemini Surfactants, and Associated Methods - Methods and compositions are provided that include degradable gemini surfactants including degradable gemini surfactants. Methods of use include subterranean operations, especially those involving the placement of resin systems, formation of emulsions (e.g., emulsified acids, emulsified fracturing fluids, drilling fluids, etc.), and in the formation of surfactant gelled fluids. Such treatments include, but are not limited to, drilling, stimulation treatments (e.g., fracturing treatments, acidizing treatments), and completion operations (e.g., sand control treatments like gravel packing). | 03-24-2011 |
20120270758 | Degradable Surfactants, Including Degradable Gemini Surfactants, and Associated Methods - A subterranean treatment fluid comprising a degradable gemini surfactant composition described by the following formula: | 10-25-2012 |
20130130946 | STABILIZATION OF EMULSIONS CONTAINING RESINOUS MATERIAL FOR USE IN THE FIELD OF OIL OR GAS WELL TREATMENTS - Emulsions for use in a well including: (a) a water-insoluble resinous material; (b) water; and (c) an emulsifier, wherein the emulsifier comprises a non-ionic, a cationic, or a zwitterionic emulsifier; wherein the continuous phase of the emulsion comprises the water; wherein a dispersed phase of the emulsion comprises the resinous material; wherein the dispersed phase is in the form of droplets having a size distribution range such that at least 50% of the droplets have a size of 0.5 micrometers-500 micrometers; wherein the resinous material of the droplets is in a concentration of at least 5% by weight of the water; and wherein the composition of the droplets has a viscosity of less than 2,000 Poise measured at 20° F. Methods include the steps of: (a) forming an emulsion described above; and (b) introducing the emulsion into a portion of a subterranean formation. | 05-23-2013 |
Patent application number | Description | Published |
20100229012 | MICROPROCESSOR THAT PERFORMS ADAPTIVE POWER THROTTLING - A microprocessor that performs adaptive power throttling includes a calculation unit that calculates an average power consumed by the microprocessor over a most recent predetermined sample time and determines whether the average power is less than a predetermined maximum power value. A power management unit controls the microprocessor to conditionally operate at a predetermined frequency if the average power is less than the predetermined maximum power value. The predetermined frequency is a frequency at which the microprocessor may consume more than the predetermined maximum power value. The predetermined maximum power value and sample time are specified to achieve power and/or thermal design goals of a system in which the microprocessor operates. The predetermined maximum power and/or sample time values are programmable by system software. To maintain a running average power value, a counter is incremented, both in sleeping and running states, by different increments depending upon the current performance point. | 09-09-2010 |
20110035616 | DETECTION OF UNCORRECTABLE RE-GROWN FUSES IN A MICROPROCESSOR - A microprocessor includes a first plurality of fuses, a predetermined number of which are selectively blown. Control values are provided from the first plurality of fuses to circuits of the microprocessor to control operation of the microprocessor. The microprocessor also includes a second plurality of fuses, blown with the predetermined number of the first plurality of fuses that are blown. In response to being reset, the microprocessor is configured to: read the first plurality of fuses and count a number of them that are blown; read the predetermined number from the second plurality of fuses; compare the counted number with the predetermined number read from the second plurality of fuses; and prevent itself from fetching and executing user program instructions if the number counted from reading the first plurality of fuses does not equal the predetermined number read from the second plurality of fuses. | 02-10-2011 |
20110035623 | DETECTION OF FUSE RE-GROWTH IN A MICROPROCESSOR - A microprocessor includes a first plurality of fuses, a predetermined number of which are selectively blown. Control values are provided from the fuses to circuits of the microprocessor to control operation thereof. A second plurality of fuses are blown with the predetermined number of the first plurality of fuses that are blown and a Boolean complement of the predetermined number. In response to being reset, the microprocessor: reads the predetermined number and the Boolean complement of the predetermined number from the second plurality of fuses, Boolean complements the predetermined number read from the second plurality of fuses to generate a result, compares the result with the Boolean complement of the predetermined number read from the second plurality of fuses, and prevent itself from fetching and executing user program instructions if the result does not equal the Boolean complement of the predetermined number read from the second plurality of fuses. | 02-10-2011 |
20120005514 | MULTICORE PROCESSOR POWER CREDIT MANAGEMENT IN WHICH MULTIPLE PROCESSING CORES USE SHARED MEMORY TO COMMUNICATE INDIVIDUAL ENERGY CONSUMPTION - A microprocessor includes two or more processing cores each configured to compute a first value in response to detecting a power event. The first value represents an amount of energy the core consumed during a time interval leading up to the event. The length of the time interval is predetermined. Each core reads from the memory one or more second values that represent an amount of energy the other cores consume during approximately the time interval. The second values were previously computed and written to the memory by the other cores. Each core adjusts its operating frequency based on the first and second values. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined length of time without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the cores to operate. | 01-05-2012 |
20120047377 | MULTICORE PROCESSOR POWER CREDIT MANAGEMENT BY DIRECTLY MEASURING PROCESSOR ENERGY CONSUMPTION - A microprocessor includes an input that receives an indication of the amount of instantaneous power being supplied to the microprocessor by an external power source. The microprocessor includes a plurality of processing cores that each receive the indication from the input and responsively determine an amount of energy consumed by the microprocessor during a preceding period. The period is a predetermined length of time. Each processing core operates at a frequency above a predetermined frequency in response to determining that the amount of energy consumed by the microprocessor during the preceding period is less than a predetermined amount of energy. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined length of time without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the two or more processing cores to operate. | 02-23-2012 |
20120047385 | MULTICORE PROCESSOR POWER CREDIT MANAGEMENT TO ALLOW ALL PROCESSING CORES TO OPERATE AT ELEVATED FREQUENCY - A microprocessor includes two or more processing cores each configured to determine, at each of succeeding instances in time, an amount of energy consumed by the microprocessor during a period preceding the instance in time. The period is predetermined. Each core also operates at a frequency above a predetermined frequency in response to determining the amount of energy consumed is less than a predetermined amount of energy. All of the cores may operate above the predetermined frequency simultaneously until one of the cores determines the microprocessor has consumed more than the predetermined amount of energy during the period preceding the instance in time. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined period without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the cores to operate. | 02-23-2012 |
20120166764 | DYNAMIC AND SELECTIVE CORE DISABLEMENT AND RECONFIGURATION IN A MULTI-CORE PROCESSOR - Dynamically reconfigurable multi-core microprocessors and associated methods are provided. A multi-core microprocessor is provided that supports the ability of system software to disable, or kill, selected cores in such a way that they do not cause drag on the processor bus shared with the other cores. Another multi-core microprocessor is provided that supports reconfiguration of an inter-core coordination system of the microprocessor, wherein cores may be selectively designated as masters for purposes of driving signals onto an inter-core communication wire. | 06-28-2012 |
20150046680 | DYNAMIC AND SELECTIVE CORE DISABLEMENT AND RECONFIGURATION IN A MULTI-CORE PROCESSOR - A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires, extrinsic to a system bus connected to a chipset, which facilitate non-system-bus inter-core communications. At least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of structuring sideband-based inter-core communications. The method includes determining an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core, and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated. Each core is configured to conditionally drive a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core. | 02-12-2015 |
20150067214 | SINGLE-CORE WAKEUP MULTI-CORE SYNCHRONIZATION MECHANISM - A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep. | 03-05-2015 |
20150067219 | DYNAMIC DESIGNATION OF THE BOOTSTRAP PROCESSOR IN A MULTI-CORE MICROPROCESSOR - A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor. | 03-05-2015 |
20150067263 | SERVICE PROCESSOR PATCH MECHANISM - A microprocessor includes a plurality of processing cores, a service processing unit and a memory accessible by both the service processing unit and the plurality of processing cores. At least one of the plurality of processing cores is configured to write a patch to the memory. The patch comprises one or more instructions to be fetched from the memory and executed by the service processing unit after written to the memory by the at least one of the plurality of processing cores. | 03-05-2015 |
20150067306 | INTER-CORE COMMUNICATION VIA UNCORE RAM - A microprocessor includes a plurality of processing cores and an uncore random access memory (RAM) readable and writable by each of the plurality of processing cores. Each core of the plurality of processing cores comprises microcode run by the core that implements architectural instructions of an instruction set architecture of the microprocessor. The microcode is configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores. | 03-05-2015 |
20150067307 | PROPAGATION OF UPDATES TO PER-CORE-INSTANTIATED ARCHITECTURALLY-VISIBLE STORAGE RESOURCE - A microprocessor a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource. A first core of the plurality of processing cores is configured to encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction. The first core is further configured to, in response to encountering the architectural instruction, provide the value to each of the other of the plurality of processing cores and update the respective architecturally-visible storage resource of the first core with the value. Each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction. | 03-05-2015 |
20150067318 | SELECTIVE DESIGNATION OF MULTIPLE CORES AS BOOTSTRAP PROCESSOR IN A MULTI-CORE MICROPROCESSOR - A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate multiple of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate a single processing core of the plurality of processing cores to be the bootstrap processor. | 03-05-2015 |
20150067666 | PROPAGATION OF MICROCODE PATCHES TO MULTIPLE CORES IN MULTICORE MICROPROCESSOR - A microprocessor includes a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode. A first core of the plurality of processing cores is configured to encounter an instruction that instructs the first core to apply a microcode patch. The first core of the plurality of processing cores is further configured to, in response to encountering the instruction, inform each core of the other of the plurality of processing cores of the microcode patch and apply the microcode patch to the hardware of the first core. Each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to the hardware of the core, in response to being informed by the first core. | 03-05-2015 |
20150212947 | DYNAMIC CACHE ENLARGING BY COUNTING EVICTIONS - A microprocessor includes a cache memory and a control module. The control module makes the cache size zero and subsequently make it between zero and a full size of the cache, counts a number of evictions from the cache after making the size between zero and full and increase the size when the number of evictions reaches a predetermined number of evictions. Alternatively, a microprocessor includes: multiple cores, each having a first cache memory; a second cache memory shared by the cores; and a control module. The control module puts all the cores to sleep and makes the second cache size zero and receives a command to wakeup one of the cores. The control module counts a number of evictions from the first cache of the awakened core after receiving the command and makes the second cache size non-zero when the number of evictions reaches a predetermined number of evictions. | 07-30-2015 |