Patent application number | Description | Published |
20110084327 | 3-D ELECTRICALLY PROGRAMMABLE AND ERASABLE SINGLE-TRANSISTOR NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile memory device includes a source region, a drain region, and a channel region therebetween. The channel region has a length extending from the source region to the drain region and a channel width in the direction perpendicular to the channel length direction. The device includes a floating gate positioned between the source and the drain in the channel length direction. The width of the floating gate is less than the channel width. A control gate covers a top surface and a side surface of the floating gate. The control gate also overlies an entirety of the channel region. Erasure of the cell is accomplished by Fowler-Nordheim tunneling from the floating gate to the control gate. Programming is accomplished by electrons migrating through an electron concentration gradient from a channel region underneath the control gate into a channel region underneath the floating gate and then injecting into the floating gate. | 04-14-2011 |
20110163369 | SURROUNDING STACKED GATE MULTI-GATE FET STRUCTURE NONVOLATILE MEMORY DEVICE - Nonvolatile memory devices having a low off state leakage current and an excellent data retention time characteristics. The present invention provides a surrounding stacked gate fin field effect transistor nonvolatile memory structure comprising a silicon-on-insulator substrate of a first conductivity type and a fin active region projecting from an upper surface of the insulator. The structure further includes a tunnel oxide layer formed on the fin active region and a first gate electrode disposed on the tunnel oxide layer and upper surface of the insulator. Additionally, the structure includes an oxide/nitride/oxide (ONO) composite layer formed on the first gate electrode, a second gate electrode formed on the ONO composite layer and patterned so as to define a predetermined area of the ONO composite layer. The structure further includes a dielectric spacer formed on a sidewall of the second gate electrode and source/drain regions formed in the fin active region on both sides of the second gate electrode. | 07-07-2011 |
20110220990 | SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT - A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device. | 09-15-2011 |
20130228860 | SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT - A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device. | 09-05-2013 |
20150194522 | SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT - A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device. | 07-09-2015 |