Patent application number | Description | Published |
20100036459 | SIGNALING IN A MEDICAL IMPLANT BASED SYSTEM - Signaling in a medical implant based system. A method includes transmitting bits modulated with a predefined sequence in a band of channels by a first medical transceiver. The method includes detecting the predefined sequence by a second medical transceiver. The method also includes performing predetermined action if the predefined sequence is detected. In one example, the predetermined action includes determining presence of a signal. | 02-11-2010 |
20120106602 | Signaling in a Medical Implant Based System - Signaling in a medical implant based system. A method includes transmitting bits modulated with a predefined sequence in a band of channels by a first medical transceiver. The method includes transmitting bits modulated with a first predefined sequence of a plurality of predefined sequences by a first medical transceiver. The first predefined sequence is detected by a second medical transceiver when the second medical transceiver enters into an active state. A predetermined action is preformed if the first predefined sequence is detected. | 05-03-2012 |
20130156016 | WIRELESS NETWORK SYSTEMS - Several wireless network systems are disclosed. In an embodiment, a wireless network system includes at least two access points and a distributed set of devices communicatively associated with the at least two access points. Each device from among the distributed set of devices comprises a pair of wireless stations and each wireless station from among the pair of wireless stations is configured to transmit data associated with an alert situation to a distinct access point from among the at least two access points. A communication between one or more access points from among the at least two access points and one or more wireless stations from among the pairs of wireless stations corresponding to the distributed set of devices is synchronized based on a timing synchronization information shared by at least two basic service sets (BSSs) corresponding to the at least two access points. | 06-20-2013 |
20140062734 | ASYNCHRONOUS ANALOG-TO-DIGITAL CONVERTER - A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. If the comparison result remains substantially the same for a predetermined interval, an ADC is enabled to generate a second comparison result at a sampling instant. A second time stamp that corresponds to the sampling instant is generated. The second comparison result and a second time stamp corresponding to the first comparison result are registered, and a second portion of the digital signal is generated from the second comparison result. | 03-06-2014 |
20140062735 | ASYNCHRONOUS ANALOG-TO-DIGITAL CONVERTER HAVING ADAPATIVE REFERENCE CONTROL - A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. At least one of the first and second reference signals is adjusted. A second comparison result is generated if the analog signal reaches an adjusted one of the first and second reference signals within a predetermined interval, and a second portion of the digital signal is generated from the second comparison result. | 03-06-2014 |
20140062751 | ASYNCHRONOUS ANALOG-TO-DIGITAL CONVERTER HAVING RATE CONTROL - An apparatus is provided. A comparison circuit is configured to receive an analog signal. A reference circuit is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC) is coupled to the comparison circuit. A timer is coupled to the comparison circuit. A rate control circuit is coupled to the conversion circuit. An output circuit is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal. | 03-06-2014 |
20140247171 | ASYNCHRONOUS SAMPLING USING DYNAMICALLY CONFIGURABLE VOLTAGE POLLING LEVELS - A method, comprising: receiving an analog input; determining an upper outer rail and a lower outer rail as polling values to be used by voltage comparators; blanking at least three comparators; determining which two of the at least three comparators are closest to the input analog voltage levels; defining the two comparators which are closest to the analog input signal to be the next comparators of the next sampling process; assigning a remaining comparator at a voltage level in between the new top and bottom voltage levels; enabling the outer rails, but blanking the inner rail; progressively narrowing down the voltage range spanned by the two outer comparators; and generating a 2-tuple value of an asynchronous voltage comparator crossing. | 09-04-2014 |
20140247172 | ASYNCHRONOUS SAMPLING USING A DYNAMICALLY ADUSTABLE SNAPBACK RANGE - A snapout calculator, and wherein the snapout calculator determines where the reference levels for the various comparators shall be placed after each asynchronous sample is generated. | 09-04-2014 |
20140247173 | ASYNCHRONOUS TO SYNCHRONOUS SAMPLING USING AKIMA ALGORITHM - A method, comprising: selecting three Two-Tuples before and three after a selected synchronous ADC conversion point; calculating the coefficients of a third order polynomial based on the value of the previous time asynchronous sample, the time difference between the asynchronous samples surrounding the selected sample, and the five linear slopes of the line segments between the three points before and the points after the selected synchronous sample point, including the slope of the selected point; evaluating the third order polynomial at the synchronous time instant; generating the synchronous ADC value based on this calculation; and using the ADC value as the desired voltage level of the synchronous sample, wherein the synchronous ADC value is generated based on this calculation. | 09-04-2014 |
20140247174 | ASYNCHRONOUS TO SYNCHRONOUS SAMPLING USING MODIFIED AKIMA ALGORITHM - A method, comprising: selecting two Two-Tuples before and two after a selected synchronous ADC conversion point; calculating the coefficients of a third order polynomial based on the value of the previous time asynchronous sample, the time differences between each of the asynchronous samples surrounding the selected sample, and the three linear slopes of the line segments between the two points before and the points after the selected synchronous sample point, including the slope of the selected point; evaluating the third order polynomial at the synchronous time instant; generating the synchronous ADC value based on this calculation; and using the ADC value as the desired voltage level of the synchronous sample, wherein the synchronous ADC value is generated based on this calculation. | 09-04-2014 |
20140247175 | ASYNCHRONOUS TO SYNCHRONOUS SAMPLING USING AN AUGMENTED LEAST SQUARES SOLVER - A method, comprising: receiving a plurality of 2-tuples of asynchronously sampled inputs at an asynchronous to synchronous reconstructor; performing a coarse asynchronous to synchronous conversion using the plurality of 2-tuples to generate a plurality of low precision synchronous outputs; generating a high precision synchronous output, z | 09-04-2014 |
20140247176 | EXTENSION OF ADC DYNAMIC RANGE USING POST-PROCESSING LOGIC - An apparatus, comprising: an analog to digital converter including: a clipping detector; and a post-processor, wherein the post processor generates synchronous values of clipped data based on non-clipped values of non-clipped data. | 09-04-2014 |