Fujiwara, Yokohama
Daisuke Fujiwara, Yokohama JP
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20100131701 | NONVOLATILE MEMORY DEVICE WITH PREPARATION/STRESS SEQUENCE CONTROL - Provided is a nonvolatile memory device which includes a command buffer configured to receive and store a sequence of first and second commands, a memory including an array of nonvolatile memory cells, and an operation controller configured to control the execution of first and second operations in the memory as respectively defined by the first and second commands, wherein each one of the first and second operations comprises a preparation sequence followed by a stress sequence, and execution of the preparation sequence for the second operation is parallel with the stress sequence of the first operation. | 05-27-2010 |
20140075266 | ERROR CHECK AND CORRECTION CIRCUIT AND SEMICONDUCTOR MEMORY - An error check and correction circuit includes a Chien search unit. The Chien search unit includes a calculation circuit and a plurality of Chien search circuits. The calculation circuit is configured to calculate a first bit stream by multiplying a value of (n−k) bits by a plurality of elements and a second bit stream by multiplying a value of k bits by the plurality of elements. The plurality of Chien search circuits configured to calculate the element by connecting the first bit stream and the second bit stream, and substitute the calculated element into the error correction search equation. | 03-13-2014 |
20140089768 | ERROR LOCATION SEARCH CIRCUIT, AND ERROR CHECK AND CORRECTION CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - Provided is an error check and correction (ECC) circuit which includes a Chien search unit configured to determine whether there is an error in a data string. The Chien search unit includes a circuit configured to calculate a first bit string by multiplying a plurality of elements of Galois Field GF(2 | 03-27-2014 |
20140108895 | ERROR CORRECTION CODE CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - The ECC circuit includes a Chien search unit configured to determine whether there is an error in each bit of a data sequence. The Chien search unit selects a coefficient of a nonlinear term from among terms of an error locator polynomial as a nonlinear coefficient, separates the error locator polynomial into a first location equation including only linear terms and a second location equation including only nonlinear terms, determines a third location equation by dividing the first location equation by the nonlinear coefficient, determines a fourth location equation by dividing the second location equation by the nonlinear coefficient, and determines whether there is an error for each of the bits by performing an XOR operation on a result of the third location equation using the substitution value and a result of the fourth location equation using an arbitrary element of the error locator polynomial as a substitution value. | 04-17-2014 |
Ikuo Fujiwara, Yokohama JP
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20150136952 | NOISE REMOVING DEVICE AND IMAGING DEVICE - According to an embodiment, a noise removing device includes a first difference detector and a second difference detector. The first difference detector detects a difference between a first reset signal at a first timing and a second reset signal at a second timing after a predetermined period of time has elapsed from the first timing. The second difference detector subtracts the difference detected by the first difference detector from a main signal between the first reset signal and the second reset signal, and outputs a subtraction result. | 05-21-2015 |
20150270314 | SOLID-STATE IMAGING DEVICE - According to one embodiment, a solid-state imaging device includes: a first inorganic photoelectric converter; a semiconductor substrate that includes a light-receiving face to which light is to be incident and a circuit-formed surface on which a circuit including a readout circuit is formed, the light-receiving face facing the first inorganic photoelectric converter, the semiconductor substrate including a second inorganic photoelectric converter thereinside; and a first part including a microstructure arranged between the first inorganic photoelectric converter and the second inorganic photoelectric converter. | 09-24-2015 |
Kazuma Fujiwara, Yokohama JP
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20150261464 | MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - According to an embodiment, a controller transfers, when first data in second management unit larger than a first management unit is stored in a second buffer, the first data stored in the second buffer to a first host through a first port. After the transfer, the controller deletes second data stored in the first buffer, the second data being the same data as the transferred first data and stores second read data following the first read data in the first buffer and the second buffer in the first management unit. | 09-17-2015 |
Kazunori Fujiwara, Yokohama JP
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20150106049 | MOTION DETECTION DEVICE, ELECTRONIC DEVICE, MOTION DETECTION METHOD, AND PROGRAM STORAGE MEDIUM - A motion detection device includes: an acceleration detection unit, a separating unit, a gravity axis determination unit, and a motion detection unit. The acceleration detection unit detects acceleration components of each axis of a three-dimensional rectangular coordinate system of acceleration acting on the acceleration detection unit and outputs sets of acceleration component data. The separating unit separates the outputted sets of acceleration component data into stationary components and motion components. The gravity axis determination unit determines an axis whose separated stationary component is the largest to be a gravity axis. The motion detection unit detects, if an axis corresponding to a largest motion component showing a largest value of the separated motion components is an axis other than the determined gravity axis, a motion axis of the acceleration detection unit on the basis of the largest motion component. | 04-16-2015 |
Noriki Fujiwara, Yokohama JP
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20100100604 | CACHE CONFIGURATION SYSTEM, MANAGEMENT SERVER AND CACHE CONFIGURATION MANAGEMENT METHOD - A cache configuration management system capable of lightening workloads of estimation of a cache capacity in virtualization apparatus and/or cache assignment is provided. In a storage system having application servers, storage devices, a virtualization apparatus for letting the storage devices be distinctly recognizable as virtualized storages, and a storage management server, the storage management server predicts a response time of the virtualization apparatus with respect to a application server from cache configurations and access performances of the virtualization apparatus and storage device and then evaluates the presence or absence of the assignment to a virtual volume of internal cache and a predictive performance value based on a to-be-assigned capacity to thereby perform judgment of the cache capacity within the virtualization apparatus and estimation of an optimal cache capacity, thus enabling preparation of an internal cache configuration change plan. | 04-22-2010 |
Shinichi Fujiwara, Yokohama JP
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20130061901 | THERMOELECTRIC CONVERTING MODULE AND MANUFACTURING METHOD THEREOF - Provided is a high temperature thermoelectric converting module including a plurality of p type thermoelectric elements; a plurality of n type thermoelectric elements; a plurality of electrodes; and a lead line. The plurality of p type thermoelectric elements, the plurality of n type thermoelectric elements, and the plurality of electrodes are electrically serially connected to each other, a pair of connecting lines that connects the lead line to one of the plurality of electrodes to output to the outside is further included, at least one electrode which is disposed at the high temperature side and the plurality of p type and n type thermoelectric elements are bonded with an intermediate layer therebetween. The plurality of p type and n type thermoelectric elements contain silicon as a component and the intermediate layer is formed as a layer containing aluminum and silicon and components other than silicon of the thermoelectric elements. | 03-14-2013 |
Shisei Fujiwara, Yokohama JP
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20090292856 | INTERSERVER COMMUNICATION MECHANISM AND COMPUTER SYSTEM - An interserver communication mechanism which can eliminate the need for preparing an external I/O device for each of physical servers for communication between the physical servers and can avoid generation of overhead caused by protocol conversion. A plurality of physical servers are connected to the interserver communication mechanism via I/O link and I/O switch. The interserver communication mechanism has a read instruction generator for issuing an instruction to access data of the physical servers and a write instruction generator for transmitting the read data to the other server. Data transfer between the physical servers is carried out in the interior of the interserver communication mechanism by reading out data from a data transmission originator, writing the read data to a transmission destination as it is, and directly turning back the data at the interserver communication mechanism. | 11-26-2009 |
20110016201 | MULTI NODE SERVER SYSTEM - A server system has, in addition to extensibility of scale-out type of a braid server system, extensibility of scale-up type by making SMP coupling among nodes. Each node has a unit for SMP coupling to other nodes. A module management unit responds to system configuration information to switch between a mode in which the node operates singularly as a braid server and a mode in which the node operates as a constituent module of an SMP server. Links among individual nodes are laid through equidistant wiring lines on a back plane and additionally a loop wiring line having a length equal to that of the inter-node link on the back plane is also laid in each node, thereby setting up synchronization among the nodes. Synchronization of reference clocks for SMP coupled nodes is also established. | 01-20-2011 |
Susumu Fujiwara, Yokohama JP
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20090040789 | LIGHTING DEVICE - In the lighting device, cylindrical lenses are provided on a reflection surface side of a light guide plate, and the adjacent cylindrical lenses are connected by a concaved curved surface. | 02-12-2009 |
Yoshihiro Fujiwara, Yokohama JP
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20150362861 | DEVELOPING DEVICE, IMAGE FORMING APPARATUS, AND PROCESS CARTRIDGE - A developing device includes a developer bearer to carry developer to a developer range where the developer bearer faces a latent image bearer, a development casing forming a developer storing part storing the developer to supply to the surface of developer bearer, a developer through opening communicating a space in where the developer bearer is disposed and the developer storing part, a cover sheet covering the developer through opening at the developing casing, and when the cover sheet is removed, the developer pass through the developer through opening, a sheet collecting shaft to collect the cover sheet by rotating, and a transmitting mechanism to transmit a force for rotating to the sheet collecting shaft. The transmitting mechanism does not transmit the force to the collecting shaft after the cover sheet is collected. | 12-17-2015 |