Patent application number | Description | Published |
20100087017 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE - It is intended to produce a semiconductor device with a stable gate length, using an end-point detection process based on monitoring a plasma emission intensity during dry etching for setting a gate length. A semiconductor device production method of the present invention comprises the steps of forming a first dielectric or gate conductive film to allow a pillar-shaped semiconductor layer to be buried therein; flattening the first dielectric or gate conductive film while detecting an end-point using a stopper formed on top of the pillar-shaped semiconductor layer; forming a second dielectric or gate conductive film; etching the second dielectric or gate conductive film and calculating an etching rate during the etching; and detecting an end-point of etching of the first dielectric or gate conductive film, based on the etching rate of the second dielectric or gate conductive film during etching-back of the second dielectric or gate conductive film, to control an etching amount of the first dielectric or gate conductive film. | 04-08-2010 |
20100102362 | SOLID-STATE IMAGE PICKUP ELEMENT, SOLID-STATE IMAGE PICKUP DEVICE AND PRODUCTION METHOD THEREFOR - It is intended to provide a solid-state image pickup element capable of reducing an area of a read channel to increase a ratio of a surface area of a light-receiving section to the overall surface area of one pixel. The solid-state image pickup element comprises a first-conductive type planar semiconductor layer formed on a second-conductive type planar semiconductor layer, a hole portion formed in the first-conductive type planar semiconductor layer to define a hole therein, a first-conductive type high-concentration impurity region formed in a bottom wall of the hole portion, a first-conductive type high-concentration impurity-doped element isolation region formed in a part of a sidewall of the hole portion and connected to the first-conductive type high-concentration impurity region, a second-conductive type photoelectric conversion region formed beneath the first-conductive type high-concentration impurity region and in a part of a lower region of the remaining part of the sidewall of the hole portion, and adapted to undergo a change in charge amount upon receiving light, a transfer electrode formed on the sidewall of the hole portion through a gate dielectric film, a second-conductive type CCD channel region formed in a top surface of the first-conductive type planar semiconductor layer and in a part of an upper region of the remaining part of the sidewall of the hole portion, and a read channel formed in a region of the first-conductive type planar semiconductor layer sandwiched between the second-conductive type photoelectric conversion region and the second-conductive type CCD channel region. | 04-29-2010 |
20100142257 | SEMICONDUCTOR STORAGE DEVICE | 06-10-2010 |
20100187600 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer. | 07-29-2010 |
20100187601 | SEMICONDUCTOR DEVICE - A hermetic compressor includes a closed vessel for storing lubricating oil, an electric-driving element, and a compressing element driven by the electric-driving element. The compressing element includes a cylinder block forming a compression chamber, a piton that reciprocates inside the compression chamber, and an oiling device for supplying the lubricating oil to an outer circumference of the piston. A first oil groove is concavely formed on the outer circumference of the piston, and a second oil groove is concavely formed on a side opposite to the compression chamber relative to the first oil groove. The second oil groove has a spatial volume same or greater than that of the first oil groove. An expanded clearance portion is provided such that a clearance between the piston and the cylindrical hole portion broadens from a top dead point to a bottom dead point. | 07-29-2010 |
20100194438 | SEMICONDUCTOR DEVICE - It is intended to provide a semiconductor device which comprises an SGT-based, highly-integrated, high-speed, at least two-stage CMOS inverter cascade circuit configured to allow a pMOS SGT to have a gate width two times greater than that of an nMOS SGT. A semiconductor device of the present invention comprises a CMOS inverter cascade circuit having at least two-stage CMOS inverter, wherein: a first CMOS inverter includes two pMOS SGT arranged at respective ones of an intersection of the 1st row and the 1st column and an intersection of the 2nd row and the 1st column, and an nMOS SGT arranged at an intersection of the 1st row and the 2nd column; and a second CMOS inverter includes two pMOS SGT arranged at respective ones of an intersection of the 1st row and the 3rd column and an intersection of the 2nd row and the 3rd column, and an nMOS SGT arranged at an intersection of the 2nd row and the 2nd column. An output terminal line is connected to an input terminal line, wherein the output terminal line is arranged to interconnect a drain diffusion layer of each of the two SGTS at respective ones of the intersection of the 1st row and the intersection of the 2nd row and the 1st column and the 1st column, and a drain diffusion layer of the SGT at the intersection of the 1st row and the 2nd column, through an island-shaped semiconductor lower layer, and the an input terminal line is arranged to interconnect a gate of each of the two SGTs at respective ones of the intersection of the 1st row and the 3rd column and the intersection of the 2nd row and the 3rd column, and a gate of the SGT at and the intersecting of the 2nd row and 2nd column. | 08-05-2010 |
20100197048 | METHOD OF PRODUCING SEMICONDUCTOR - In a conventional SGT production method, during dry etching for forming a pillar-shaped silicon layer and a gate electrode, an etching amount cannot be controlled using an end-point detection process, which causes difficulty in producing an SGT while stabilizing a height dimension of the pillar-shaped silicon layer, and a gate length. In an SGT production method of the present invention, a hard mask for use in dry etching for forming a pillar-shaped silicon layer is formed in a layered structure comprising a first hard mask and a second hard mask, to allow the end-point detection process to be used during the dry etching for the pillar-shaped silicon layer. In addition, a gate conductive film for use in dry etching for forming a gate electrode is formed in a layered structure comprising a first gate conductive film and a second gate conductive film, to allow the end-point detection process to be used during the dry etching for the gate electrode. | 08-05-2010 |
20100200731 | SOLID-STATE IMAGING DEVICE - It is intended to provide a CMOS image sensor with a high degree of pixel integration. A solid-state imaging device comprises a signal line ( | 08-12-2010 |
20100200913 | SEMICONDUCTOR STORAGE DEVICE - It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in an E/R type 4T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using four MOS transistors and two load resistor elements, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer, and each of the load resistor elements is made of polysilicon and formed on the planar silicon layer. | 08-12-2010 |
20100203714 | SEMICONDUCTOR STORAGE DEVICE - It is intended to provide a semiconductor device having a reduced thickness of a silicon nitride film on an outer periphery of a gate electrode of an SGT. A semiconductor device of the present invention is constructed using a MOS transistor which has a structure where a drain, a gate and a source are arranged in a vertical direction with respect to a substrate, and the gate is formed to surround a pillar-shaped semiconductor layer. The semiconductor device comprises: a silicide layer formed in an upper surface of each of upper and lower diffusion layers formed in upper and underneath portions of the pillar-shaped semiconductor layer, in a self-alignment manner, wherein the silicide layer is formed after forming a first dielectric film on a sidewall of the pillar-shaped semiconductor layer to protect the sidewall of the pillar-shaped semiconductor layer during formation of the silicide layer; and a second dielectric film formed, after forming the silicide layer and then removing the first dielectric film, in such a manner as to cover a source/drain region formed in the underneath portion of the pillar-shaped semiconductor layer, the gate electrode formed on the sidewall of the pillar-shaped semiconductor layer, and a source/drain region formed on the upper portion of the pillar-shaped semiconductor layer. | 08-12-2010 |
20100207172 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SEMICONDUCTOR STRUCTURE - In contrast to a conventional planar CMOS technique in design and fabrication for a field-effect transistor (FET), the present invention provides an SGT CMOS device formed on a conventional substrate using various crystal planes in association with a channel type and a pillar shape of an FET, without a need for a complicated device fabrication process. Further, differently from a design technique of changing a surface orientation in each planar FET, the present invention is designed to change a surface orientation in each SGT to achieve improvement in carrier mobility. Thus, a plurality of SGTs having various crystal planes can be formed on a common substrate to achieve a plurality of different carrier mobilities so as to obtain desired performance. | 08-19-2010 |
20100207199 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - The method includes the steps of: forming a planar semiconductor layer on an oxide film formed on a substrate and then forming a pillar-shaped first-conductive-type semiconductor layer on the planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode made of a metal, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming a sidewall-shaped dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer. | 08-19-2010 |
20100207200 | SEMICONDUCTOR DEVICE - It is intended to solve a problem of increase in power consumption and reduction in operating speed due to an increase in parasitic capacitance of a surrounding gate transistor (SGT) as a three-dimensional semiconductor device, to provide an SGT achieving an increase in speed and power consumption reduction in a semiconductor circuit. The semiconductor device comprises a second-conductive type impurity region ( | 08-19-2010 |
20100207201 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - It is intended to provide a semiconductor device comprising a circuit which has a connection between one of a drain region and a source region of a first MOS transistor and one of a drain region and a source region of a second MOS transistor. The semiconductor device comprises: a substrate; a dielectric film on the substrate; and a planar semiconductor layer formed on the on-substrate dielectric film, wherein: the first MOS transistor includes a first drain or source region formed in the planar semiconductor layer, a first pillar-shaped semiconductor layer formed on the planar semiconductor layer, a second source or drain region formed in an upper portion of the first pillar-shaped semiconductor layer, and a first gate electrode formed in such a manner that the first gate electrode surrounds a sidewall of the first pillar-shaped semiconductor layer through a first dielectric film; and the second MOS transistor includes a third drain or source region formed in the planar semiconductor layer, a second pillar-shaped semiconductor layer formed on the planar semiconductor layer, a fourth source or drain region formed in an upper portion of the second pillar-shaped semiconductor layer, and a second gate electrode formed in such a manner that the second gate electrode surrounds a sidewall of the second pillar-shaped semiconductor layer through a second dielectric film, and wherein a first silicide layer is formed to connect at least a part of a surface of the first drain or source region and at least a part of a surface of the third drain or source region, wherein the first silicide layer is formed in an area other than an area in which a contact for at least the first drain or source region and the third drain or source region is formed. | 08-19-2010 |
20100210079 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - It is intended to provide an SGT production method capable of obtaining a structure for reducing a resistance of a source, drain and gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor to be obtained. The method comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a dummy gate dielectric film and a dummy gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a first dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode, through a gate dielectric film; forming a first dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on each of the second-conductive-type semiconductor layers formed in the upper portion of and underneath the pillar-shaped first-conductive-type semiconductor layer; removing the dummy gate dielectric film and the dummy gate electrode and forming a high-k gate dielectric film and a metal gate electrode. | 08-19-2010 |
20100210096 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - It is intended to provide a method of producing a semiconductor device, comprising the steps of: providing a substrate on one side of which at least one semiconductor pillar stands; forming a first dielectric film to at least partially cover a surface of the at least one semiconductor pillar; forming a conductive film on the first dielectric film; removing by etching a portion of the conductive film located on a top surface and along an upper portion of a side surface of the semiconductor pillar; forming a protective film on at least a part of the top surface and the upper portion of the side surface of the semiconductor pillar; etching back the protective film to form a protective film-based sidewall on respective top surfaces of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar; forming a resist pattern for forming a gate line in such a manner that at least a portion of the resist pattern is formed on the top surface of the semiconductor pillar by applying a resist and using lithography; and partially removing by etching the conductive film using the resist pattern as a mask while protecting, by the protective film-based sidewall, the portions of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar, to form a gate electrode and a gate line extending from the gate electrode. | 08-19-2010 |
20100213525 | SEMICONDUCTOR STORAGE DEVICE AND METHODS OF PRODUCING IT - The present invention provides a semiconductor storage device having a memory cell section and a peripheral circuit section each formed using one or more MOS transistors, comprising: a substrate; a dielectric film on the substrate; and a planar semiconductor layer formed on the on-substrate dielectric layer, wherein: the at least one MOS transistor in the memory cell section comprises a selection transistor, the at least one MOS transistor in the peripheral circuit section comprises a first MOS transistor and a second MOS transistor which are different in conductivity type from each other, the first MOS transistor includes a first lower drain or source region formed in the planar semiconductor layer, a first pillar-shaped semiconductor layer formed on the planar semiconductor layer, a first upper source or drain region formed in an upper portion of the first pillar-shaped semiconductor layer, and a first gate electrode formed such that the first gate electrode surrounds a sidewall of the first pillar-shaped semiconductor layer through a first dielectric film, the second MOS transistor includes a second lower drain or source region formed in the planar semiconductor layer, a second pillar-shaped semiconductor layer formed on the planar semiconductor layer, a second upper source or drain region formed in an upper portion of the second pillar-shaped semiconductor layer, and a second gate electrode formed such that the second gate electrode surrounds a sidewall of the second pillar-shaped semiconductor layer through a second dielectric film; and the selection transistor includes a third lower drain or source region formed in the planar semiconductor layer, a third pillar-shaped semiconductor layer formed on the planar semiconductor layer, a third lower source or drain region formed in an upper portion of the third pillar-shaped semiconductor layer, and a third gate electrode formed such that the third gate electrode surrounds a sidewall of the third pillar-shaped semiconductor layer through a third dielectric film, and wherein the semiconductor storage device has a first silicide layer formed thereon to connect at least a part of a surface of the first lower drain or source region of the first MOS transistor and at least a part of a surface of the second lower drain or source region of the second MOS transistor, and a second silicide layer formed on at least a part of a surface of the third lower drain or source region of the selection transistor. | 08-26-2010 |
20100213539 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; one of a drain region and a source region formed in contact with a lower part of the semiconductor pillar; a first gate formed around a sidewall of the semiconductor pillar through a first dielectric film therebetween; and an epitaxial semiconductor layer formed on a top surface of the semiconductor pillar, wherein the other of the source region and the drain region is formed so as to be at least partially in the epitaxial semiconductor layer, and wherein: the other of the source region and the drain region has a top surface having an area greater than that of the top surface of the semiconductor pillar. | 08-26-2010 |
20100219457 | SOLID-STATE IMAGING DEVICE - It is an object to provide an image sensor having a sufficiently-large ratio of a surface area of a light-receiving section to an overall surface area of one pixel. This object is achieved by a solid-state imaging device comprising: a signal line formed on a substrate; an island-shaped semiconductor arranged on the signal line; and a pixel selection line connected to a top of the island-shaped semiconductor, wherein the island-shaped semiconductor includes: a first semiconductor layer formed as a bottom portion of the island-shaped semiconductor and connected to the signal line; a second semiconductor layer formed above and adjacent to the first semiconductor layer; a gate connected to the second semiconductor layer through a dielectric film; a charge storage section comprised of a third semiconductor layer connected to the second semiconductor layer and adapted, in response to receiving light, to undergo a change in amount of electric charges therein; and a fourth semiconductor layer formed above and adjacent to the second and third semiconductor layers, and wherein the pixel selection line is comprised of a transparent conductive film, and a part of the gate is disposed inside a depression formed in a sidewall of the second semiconductor layer. | 09-02-2010 |
20100219464 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device production method, which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer on a planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode having a laminated structure of a metal film and an amorphous silicon or polysilicon film, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming first and second sidewall-shaped dielectric films on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the gate electrode; forming a contact on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; and forming a contact on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer. | 09-02-2010 |
20100219482 | SEMICONDUCTOR STORAGE DEVICE - It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in a Loadless 4T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using four MOS transistors, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer. The planar silicon layer comprises a first active region having a first conductive type, and a second active region having a second conductive type. The first and second active regions are connected to each other through a silicide layer formed in a surface of the planar silicon layer to achieve an SRAM cell having a sufficiently-small area. | 09-02-2010 |
20100219483 | SEMICONDUCTOR STORAGE DEVICE - It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in a CMOS 6T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using six MOS transistors, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer. The planar silicon layer comprises a first active region having a first conductive type, and a second active region having a second conductive type. The first and second active regions are connected to each other through a silicide layer formed in a surface of the planar silicon layer to achieve an SRAM cell having a sufficiently-small area. | 09-02-2010 |
20100244140 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - It is an object to allow an inverter to be made up using a single island-shaped semiconductor, so as to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit. The object is achieved by a semiconductor device which comprises an island-shaped semiconductor layer, a first gate dielectric film surrounding a periphery of the island-shaped semiconductor layer, a gate electrode surrounding a periphery of the first gate dielectric film, a second gate dielectric film surrounding a periphery of the gate electrode, a tubular semiconductor layer surrounding a periphery of the second gate dielectric film, a first first-conductive-type high-concentration semiconductor layer disposed on top of the island-shaped semiconductor layer, a second first-conductive-type high-concentration semiconductor layer disposed underneath the island-shaped semiconductor layer, a first second-conductive-type high-concentration semiconductor layer disposed on top of the tubular semiconductor layer, and a second second-conductive-type high-concentration semiconductor layer disposed underneath the tubular semiconductor layer. | 09-30-2010 |
20100264484 | SEMICONDUCTOR DEVICE - In a vertical transistor comprising a pillar-shaped semiconductor layer and a gate electrode formed to around the pillar-shaped semiconductor layer, it is difficult to form a transistor having a gate length greater than that of the vertical transistor. The present invention provides a semiconductor device which comprises two vertical transistors comprising first and second pillar-shaped semiconductor layers each formed on a first diffusion layer on a substrate. The vertical transistors have a common gate electrode. A first upper diffusion layer formed on a top of the first pillar-shaped semiconductor layer is connected to a source electrode, and a second upper diffusion layer formed on a top of the second pillar-shaped semiconductor layer is connected to a drain electrode. The vertical transistors are connected in series to operate as a composite transistor having a gate length two times greater than that of each of the vertical transistors. | 10-21-2010 |
20100264485 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention provides a method of manufacturing a semiconductor device, which comprises the steps of: forming a first columnar semiconductor layer on a first flat semiconductor layer; forming a first semiconductor layer of a second conductive type in a lower portion of the first columnar semiconductor layer; forming a first insulating film around a lower sidewall of the first columnar silicon layer; forming a gate insulating film and a gate electrode around the first columnar silicon layer; forming a sidewall-shaped second insulating film to surround an upper sidewall of the first columnar silicon layer; forming a semiconductor layer of a first conductive type between the first semiconductor layer of the second conductive type and a second semiconductor layer of the second conductive type; and forming a metal-semiconductor compound on an upper surface of the first semiconductor layer of the second conductive type. | 10-21-2010 |
20100270611 | SEMICONDUCTOR DEVICE INCLUDING A MOS TRANSISTOR AND PRODUCTION METHOD THEREFOR - It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; a bottom doped region formed in contact with a lower part of the semiconductor pillar; a first gate formed around a sidewall of the semiconductor pillar through a first dielectric film therebetween; and a top doped region formed so as to at least partially overlap a top surface of the semiconductor pillar, wherein the top doped region has a top surface having an area greater than that of the top surface of the semiconductor pillar. | 10-28-2010 |
20100295135 | SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD THEREFOR - In a static memory cell comprising six MOS transistors, the MOS transistors have a structure in which the drain, gate and source formed on the substrate are arranged in the vertical direction and the gate surrounds the columnar semiconductor layer, the substrate comprises a first active region having a first conductive type and a second active region having a second conductive type, and diffusion layers constructing the active regions are mutually connected via a silicide layer formed on the substrate surface, thereby realizing an SRAM cell with small surface area. In addition, drain diffusion layers having the same conductive type as a first well positioned on the substrate are surrounded by a first anti-leak diffusion layer and a second anti-leak diffusion layer having a conductive type different from the first well and being shallower than the first well, and thereby controlling leakage to the substrate. | 11-25-2010 |
20100301402 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device which is capable of preventing an increase in power consumption of an SGT, i.e., a three-dimensional semiconductor transistor, due to an increase in off-leak current. The semiconductor device comprises: a first-conductive type first silicon pillar: a first dielectric surrounding a side surface of the first silicon pillar; a gate surrounding the dielectric; a second silicon pillar provided underneath the first silicon pillar; and a third silicon pillar provided on a top of the first silicon pillar. The second silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region. The third silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar. The first-conductive type impurity region of each of the second silicon pillar and the third silicon pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type high-concentration impurity region of a respective one of the second silicon pillar and the third silicon pillar. | 12-02-2010 |
20100308422 | SEMICONDUCTOR DEVICE - The object to provide a highly-integrated SGT-based SRAM is achieved by forming an SRAM using an inverter which comprises a first island-shaped semiconductor layer, a first gate dielectric film in contact with a periphery of the first island-shaped semiconductor layer, a first gate electrode having one surface in contact with the first gate dielectric film, a second gate dielectric film in contact with another surface of the first gate electrode, a first arc-shaped semiconductor layer in contact with the second gate dielectric film, a first first-conductive-type high-concentration semiconductor layer arranged on a top of the first island-shaped semiconductor layer, a second first-conductive-type high-concentration semiconductor layer arranged underneath the first island-shaped semiconductor layer, a first second-conductive-type high-concentration semiconductor layer arranged on a top of the first arc-shaped semiconductor layer, and a second second-conductive-type high-concentration semiconductor layer arranged underneath the first arc-shaped semiconductor layer. | 12-09-2010 |
20110042740 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate. | 02-24-2011 |
20110062515 | SEMICONDUCTOR DEVICE - A first gate electrode surrounding the periphery of the first gate insulating film, a second gate insulating film surrounding the periphery of the first gate electrode, a first columnar silicon layer surrounding the periphery of the second gate insulating film, a first upper part high concentration semiconductor layer of the first conductivity type formed in the upper part of the first island-shaped silicon layer, a second lower part high concentration semiconductor layer of the first conductivity type formed in the lower part of the first island-shaped silicon layer, a first upper part high concentration semiconductor layer of the second conductivity type formed in the upper part of the first columnar silicon layer, and a second lower part high concentration semiconductor layer of the second conductivity type formed in the lower part of the first columnar silicon layer. | 03-17-2011 |
20110062521 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention comprises a first transistor and a second transistor, and functions as an inverter. The first transistor includes an island semiconductor layer, a first gate insulating film surrounding the periphery of the island semiconductor layer, a gate electrode surrounding the periphery of the first gate insulating film, p+-type semiconductor layers formed in the upper and lower part of the island semiconductor layer, respectively. The second transistor includes the gate electrode, a second gate insulating film surrounding a part of the periphery of the gate electrode, an arcuate semiconductor layer contacting a part of the periphery of the second gate insulating film, n+-type semiconductor layers formed in the upper and lower part of the arcuate semiconductor layer, respectively. A first contact electrically connects the p+-type semiconductor layer in the first transistor and the n+-type semiconductor layer in the second transistor. | 03-17-2011 |
20110062523 | SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD THEREOF - In a static memory cell composed of four MOS transistors, the transistors composing a memory cell are formed on a substrate and have a drain, gate, and source arranged vertically with the gate surrounding a columnar semiconductor layer. In this memory cell, the first diffusion layers (second diffusion layers) functioning as a first memory node (second memory node) are connected via a first silicide layer (second silicide layer) formed on their surfaces, whereby an SRAM cell having a small area is realized. Furthermore, a first anti-leak diffusion layer (second anti-leak diffusion layer) having the conductivity type opposite to the first well is formed between the first well and the first diffusion layer (second diffusion layer) having the same conductivity type as the first well so as to prevent leak to the substrate. | 03-17-2011 |
20110062529 | SEMICONDUCTOR MEMORY DEVICE - In a static memory cell configured using four MOS transistors and two load resistance elements, the MOS transistors are formed on diffusion layers formed on a substrate. The diffusion layers serve as memory nodes. The drain, gate and source of the MOS transistors are arranged in the direction orthogonal to the substrate, and the gate surrounds a columnar semiconductor layer. In addition, the load resistance elements are formed by contact plugs. In this way, it is possible to form a SRAM cell with a small area. | 03-17-2011 |
20110079841 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device which has a CMOS inverter circuit and which can accomplish high-integration by configuring an inverter circuit with a columnar structural body. A semiconductor device includes a columnar structural body which is arranged on a substrate and which comprises a p-type silicon, an n-type silicon, and an oxide arranged between the p-type silicon and the n-type silicon and running in the vertical direction to the substrate, n-type high-concentration silicon layers arranged on and below the p-type silicon, p-type high-concentration silicon layers arrange on and below the n-type silicon, an insulator which surrounds the p-type silicon, the n-type silicon, and the oxide, and which serves as a gate insulator, and a conductive body which surrounds the insulator and which serves as a gate electrode. | 04-07-2011 |
20110086460 | SOLID-STATE IMAGE PICKUP ELEMENT, SOLID-STATE IMAGE PICKUP DEVICE AND PRODUCTION METHOD THEREFOR - It is intended to provide a solid-state image pickup element capable of reducing an area of a read channel to increase a ratio of a surface area of a light-receiving section to the overall surface area of one pixel. The solid-state image pickup element comprises a first-conductive type planar semiconductor layer formed on a second-conductive type planar semiconductor layer, a hole portion formed in the first-conductive type planar semiconductor layer to define a hole therein, a first-conductive type high-concentration impurity region formed in a bottom wall of the hole portion, a first-conductive type high-concentration impurity-doped element isolation region formed in a part of a sidewall of the hole portion and connected to the first-conductive type high-concentration impurity region, a second-conductive type photoelectric conversion region formed beneath the first-conductive type high-concentration impurity region and in a part of a lower region of the remaining part of the sidewall of the hole portion, and adapted to undergo a change in charge amount upon receiving light, a transfer electrode formed on the sidewall of the hole portion through a gate dielectric film, a second-conductive type CCD channel region formed in a top surface of the first-conductive type planar semiconductor layer and in a part of an upper region of the remaining part of the sidewall of the hole portion, and a read channel formed in a region of the first-conductive type planar semiconductor layer sandwiched between the second-conductive type photoelectric conversion region and the second-conductive type CCD channel region. | 04-14-2011 |
20110089496 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD - The object to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit is achieved by forming an inverter which comprises: a first transistor including; an first island-shaped semiconductor layer; a first gate insulating film; a gate electrode; a first first-conductive-type high-concentration semiconductor layer arranged above the first island-shaped semiconductor layer; and a second first-conductive-type high-concentration semiconductor layer arranged below the first island-shaped semiconductor layer, and a second transistor including; a second gate insulating film surrounding a part of the periphery of the gate electrode; a second semiconductor layer in contact with a part of the periphery of the second gate insulating film; a first second-conductive-type high-concentration semiconductor layer arranged above the second semiconductor layer; and a second second-conductive-type high-concentration semiconductor layer arranged below the second semiconductor layer. | 04-21-2011 |
20110115011 | SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - The object of the invention is to provide a semiconductor device realizing high-speed operation of surrounding gate transistors (SGTs), which are three-dimensional semiconductors, by increasing the ON current of the SGTs. This object is achieved by a semiconductor element being provided in which a source, a drain and a gate are positioned in layers on a substrate, the semiconductor element being provided with: a silicon column; an insulating body surrounding the side surface of the silicon column; a gate surrounding the insulating body; a source region positioned above or below the silicon column; and a drain region positioned below or above the silicon column; wherein the contact surface of the silicon column with the source region is smaller than the contact surface of the silicon column with the drain region. | 05-19-2011 |
20110207260 | METHOD OF PRODUCING A SOLID-STATE IMAGE SENSING DEVICE INCLUDING SOLID-STATE IMAGE SENSOR HAVING A PILAR-SHAPED SEMICONDUCTOR LAYER - It is an object to provide a CCD solid-state image sensor, in which an area of a read channel is reduced and a rate of a surface area of a light receiving portion (photodiode) to an area of one pixel is increased. There is provided a solid-state image sensor, including: a first conductive type semiconductor layer; a first conductive type pillar-shaped semiconductor layer formed on the first conductive type semiconductor layer; a second conductive type photoelectric conversion region formed on the top of the first conductive type pillar-shaped semiconductor layer, an electric charge amount of the photoelectric conversion region being changed by light; and a high-concentrated impurity region of the first conductive type formed on a surface of the second conductive type photoelectric conversion region, the impurity region being spaced apart from a top end of the first conductive type pillar-shaped semiconductor layer by a predetermined distance, wherein a transfer electrode is formed on the side of the first conductive type pillar-shaped semiconductor layer via a gate insulating film, a second conductive type CCD channel region is formed below the transfer electrode, and a read channel is formed in a region between the second conductive type photoelectric conversion region and the second conductive type CCD channel region. | 08-25-2011 |
20110215381 | SOLID STATE IMAGING DEVICE - Each pixel of a solid state imaging device comprises a first semiconductor layer formed on a substrate, having a first-conductive type; a second semiconductor layer formed thereon, having a second-conductivity type; a third semiconductor layer formed in the upper side of the second semiconductor layer, having the first-conductivity type; a fourth semiconductor layer formed in the outer side of the third semiconductor layer, having the second-conductivity type; a gate conductor layer formed on the lower side of the second semiconductor layer via an insulating film; and a fifth semiconductor layer formed on the top surfaces of the second semiconductor layer and third semiconductor layer, having the second-conductivity type, wherein the fifth semiconductor layer and fourth semiconductor layer are connected to each other, and at least the third semiconductor layer, upper region of the second semiconductor layer, fourth semiconductor layer, and fifth semiconductor layer are formed in an island. | 09-08-2011 |
20110220969 | SOLID STATE IMAGING DEVICE - Each pixel of a solid state imaging device comprises: a first semiconductor layer; a second semiconductor layer; a third semiconductor layer and fourth semiconductor layer formed on the lateral side of the upper region of the second layer not to be in contact with the top surface of the second semiconductor layer; a gate conductor layer formed on the lower side of the second semiconductor layer; a conductor electrode formed on the side of the fourth semiconductor layer via an insulating film; and a fifth semiconductor layer formed on the top surface of the second semiconductor layer, wherein at least the third semiconductor layer, upper region of the second semiconductor layer, fourth semiconductor layer, and fifth semiconductor layer are formed in the shape of an island. A specific voltage is applied to the conductor electrode to accumulate holes in the surface region of the fourth semiconductor layer. | 09-15-2011 |
20110220972 | SOLID-STATE IMAGE PICKUP ELEMENT, SOLID-STATE IMAGE PICKUP DEVICE AND PRODUCTION METHOD THEREFOR - It is intended to provide a solid-state image pickup element capable of reducing an area of a read channel to increase a ratio of a surface area of a light-receiving section to the overall surface area of one pixel. The solid-state image pickup element comprises a first-conductive type planar semiconductor layer formed on a second-conductive type planar semiconductor layer, a hole portion formed in the first-conductive type planar semiconductor layer to define a hole therein, a first-conductive type high-concentration impurity region formed in a bottom wall of the hole portion, a first-conductive type high-concentration impurity-doped element isolation region formed in a part of a sidewall of the hole portion and connected to the first-conductive type high-concentration impurity region, a second-conductive type photoelectric conversion region formed beneath the first-conductive type high-concentration impurity region and in a part of a lower region of the remaining part of the sidewall of the hole portion, and adapted to undergo a change in charge amount upon receiving light, a transfer electrode formed on the sidewall of the hole portion through a gate dielectric film, a second-conductive type CCD channel region formed in a top surface of the first-conductive type planar semiconductor layer and in a part of an upper region of the remaining part of the sidewall of the hole portion, and a read channel formed in a region of the first-conductive type planar semiconductor layer sandwiched between the second-conductive type photoelectric conversion region and the second-conductive type CCD channel region. | 09-15-2011 |
20110241122 | SEMICONDUCTOR DEVICE - There is provided a high-integrated complementary metal-oxide semiconductor static random-access memory including an inverter. The inverter includes: a first pillar that is formed by integrating a first-conductivity-type semiconductor, a second-conductivity-type semiconductor, and an insulating material disposed between the first-conductivity-type semiconductor and the second-conductivity-type semiconductor, and that vertically extends with respect to a substrate; a first second-conductivity-type high-concentration semiconductor disposed on the first-conductivity-type semiconductor; a second second-conductivity-type high-concentration semiconductor disposed under the first-conductivity-type semiconductor; a first first-conductivity-type high-concentration semiconductor disposed on the second-conductivity-type semiconductor; a second first-conductivity-type high-concentration semiconductor disposed under the second-conductivity-type semiconductor; a gate insulating material formed around the first pillar; and a gate conductive material formed around the gate insulating material. | 10-06-2011 |
20110244602 | METHOD OF PRODUCING SEMICONDUCTOR - In a conventional SGT production method, during dry etching for forming a pillar-shaped silicon layer and a gate electrode, an etching amount cannot be controlled using an end-point detection process, which causes difficulty in producing an SGT while stabilizing a height dimension of the pillar-shaped silicon layer, and a gate length. In an SGT production method of the present invention, a hard mask for use in dry etching for forming a pillar-shaped silicon layer is formed in a layered structure comprising a first hard mask and a second hard mask, to allow the end-point detection process to be used during the dry etching for the pillar-shaped silicon layer. In addition, a gate conductive film for use in dry etching for forming a gate electrode is formed in a layered structure comprising a first gate conductive film and a second gate conductive film, to allow the end-point detection process to be used during the dry etching for the gate electrode. | 10-06-2011 |
20110260259 | SEMICONDUCTOR DEVICE - The CMOS inverter coupled circuit is composed of CMOS inverters using SGTs and series-connected in two or more stages. Multiple CMOS inverters share source diffusion layers on a substrate. The CMOS inverters different in the structure of a contact formed on gate wires are alternately arranged next to each other. The CMOS inverters are provided at the minimum intervals. The output terminal of a CMOS inverter is connected to the wiring layer of the next-stage CMOS inverter via the contact of the next-stage CMOS inverter. | 10-27-2011 |
20110298029 | SEMICONDUCTOR STORAGE DEVICE | 12-08-2011 |
20110298030 | SEMICONDUCTOR STORAGE DEVICE | 12-08-2011 |
20110303966 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped floating gate arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the floating gate and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the floating gate in such a manner that an inter-polysilicon insulating film is interposed between the control gate and the floating gate. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the upper, lower, and inner side surfaces of the control gate. | 12-15-2011 |
20110303973 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD - The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film. | 12-15-2011 |
20110303985 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer. | 12-15-2011 |
20120025281 | SOLID-STATE IMAGING DEVICE - A pixel includes at least first to fourth semiconductor tiers. The first semiconductor tier includes a first semiconductor region that is electrically connected to a first external circuit, a second semiconductor region, and a third semiconductor region that is isolated from the first semiconductor region by the second semiconductor region and that is electrically connected to a second external circuit. The second semiconductor tier includes a MOS transistor that has insulating films and gate conductive electrodes that are electrically connected to a third external circuit. The third semiconductor tier includes a photodiode formed of the second and fourth semiconductor regions. A junction transistor is formed in which the fourth semiconductor region serves as a gate and in which one of the first and fifth semiconductor regions serves as a drain and the other serves as a source. | 02-02-2012 |
20120025291 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the silicon substrate side, a floating gate arranged so as to surround the outer periphery of the channel region with a tunnel insulating film interposed between the floating gate and the channel region, a control gate arranged so as to surround the outer periphery of the floating gate with an inter-polysilicon insulating film interposed between the control gate and the floating gate, and a control gate line electrically connected to the control gate and extending in a predetermined direction. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the lower and inner side surfaces of the control gate and between the floating gate and the lower surface of the control gate line. | 02-02-2012 |
20120025292 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the Si substrate side, a floating gate surrounding the outer periphery of the channel region with a tunnel insulating film interposed therebetween, a control gate surrounding the outer periphery of the floating gate with an inter-polysilicon insulating film interposed therebetween, and a control gate line connected to the control gate and extending in a predetermined direction. The floating gate extends to regions below and above the control gate and to a region below the control gate line. The inter-polysilicon insulating film is interposed between the floating gate and the upper surface, lower surface, and inner side surface of the control gate and between the control gate line and a portion of the floating gate that extends to the region below the control gate line. | 02-02-2012 |
20120139035 | SEMICONDUCTOR DEVICE - A semiconductor memory device includes a static memory cell having six MOS transistors arranged on a substrate. The six MOS transistors include first and second NMOS access transistors, third and fourth NMOS driver transistors, and first and second PMOS load transistors. Each of the first and second NMOS access transistors has a first diffusion layer, a pillar-shaped semiconductor layer, and a second diffusion layer arranged vertically on the substrate in a hierarchical manner. Each of the third and fourth NMOS driver transistors has a third diffusion layer, a pillar-shaped semiconductor layer, and a fourth diffusion layer arranged vertically on the substrate in a hierarchical manner. The lengths between the upper ends of the third diffusion layers and the lower ends of the fourth diffusion layers are shorter than the lengths between the upper ends of the first diffusion layer and the lower ends of the second diffusion layers. | 06-07-2012 |
20120142154 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - An SGT production method includes forming a pillar-shaped first-conductive-type semiconductor layer and forming a second-conductive-type semiconductor layer underneath the first-conductive-type semiconductor layer. A dummy gate dielectric film and a dummy gate electrode are formed around the first-conductive-type semiconductor layer and a first dielectric film is formed on an upper region of a sidewall of the first-conductive-type semiconductor layer in contact with a top of the gate electrode. A first dielectric film is formed on a sidewall of the gate electrode and a second-conductive-type semiconductor layer is formed in an upper portion of the first-conductive-type semiconductor layer. A second-conductive-type semiconductor layer is formed in an upper portion of the first-conductive-type semiconductor layer and a metal-semiconductor compound is formed on each of the second-conductive-type semiconductor layers. The dummy gate dielectric film and the dummy gate electrode are removed and a high-k gate dielectric film and a metal gate electrode are formed. | 06-07-2012 |
20120171825 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SEMICONDUCTOR STRUCTURE - In contrast to a conventional planar CMOS technique in design and fabrication for a field-effect transistor (FET), the present invention provides an SGT CMOS device formed on a conventional substrate using various crystal planes in association with a channel type and a pillar shape of an FET, without a need for a complicated device fabrication process. Further, differently from a design technique of changing a surface orientation in each planar FET, the present invention is designed to change a surface orientation in each SGT to achieve improvement in carrier mobility. Thus, a plurality of SGTs having various crystal planes can be formed on a common substrate to achieve a plurality of different carrier mobilities so as to obtain desired performance. | 07-05-2012 |
20120181618 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A first driver transistor includes a first gate insulating film that surrounds a periphery of a first island-shaped semiconductor, a first gate electrode having a first surface that is in contact with the first gate insulating film, and first and second first-conductivity-type high-concentration semiconductors disposed on the top and bottom of the first island-shaped semiconductor, respectively. A first load transistor includes a second gate insulating film having a first surface that is in contact with a second surface of the first gate electrode, a first arcuate semiconductor formed so as to be in contact with a portion of a second surface of the second gate insulating film, and first and second second-conductivity-type high-concentration semiconductors disposed on the top and bottom of the first arcuate semiconductor, respectively. A first gate line extends from the first gate electrode and is made of the same material as the first gate electrode. | 07-19-2012 |
20120196415 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - A method of producing a semiconductor device including a MOS transistor, includes the steps of forming, on a top surface of at least one of semiconductor pillars, an epitaxial layer having a top surface larger in area than the top surface of the at least one of the semiconductor pillars and forming a source region or a drain region so as to be at least partially in the epitaxial layer. | 08-02-2012 |
20120228677 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a step of forming a conductor layer and a first semiconductor layer containing a donor impurity or an acceptor impurity on a first semiconductor substrate; a step of forming a second insulating layer so as to cover the first semiconductor layer; a step of thinning the first semiconductor substrate to a predetermined thickness; a step of forming, from the first semiconductor substrate, a pillar-shaped semiconductor having a pillar-shaped structure on the first semiconductor layer; a step of forming a first semiconductor region in the pillar-shaped semiconductor by diffusing the impurity from the first semiconductor layer; and a step of forming a pixel of a solid-state imaging device with the pillar-shaped semiconductor into which the impurity has been diffused. | 09-13-2012 |
20120264265 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - It is an object to allow an inverter to be made up using a single island-shaped semiconductor, so as to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit. The object is achieved by a semiconductor device which comprises an island-shaped semiconductor layer, a first gate dielectric film surrounding a periphery of the island-shaped semiconductor layer, a gate electrode surrounding a periphery of the first gate dielectric film, a second gate dielectric film surrounding a periphery of the gate electrode, a tubular semiconductor layer surrounding a periphery of the second gate dielectric film, a first first-conductive-type high-concentration semiconductor layer disposed on top of the island-shaped semiconductor layer, a second first-conductive-type high-concentration semiconductor layer disposed underneath the island-shaped semiconductor layer, a first second-conductive-type high-concentration semiconductor layer disposed on top of the tubular semiconductor layer, and a second second-conductive-type high-concentration semiconductor layer disposed underneath the tubular semiconductor layer. | 10-18-2012 |
20120270374 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - A method of producing a semiconductor device including a MOS transistor includes steps of forming a plurality of pillar semiconductor layers and forming a gate electrode formed around each of the pillar-shaped semiconductor layers. The method also includes steps of forming a source or drain region in an upper portion of each of the pillar-shaped semiconductor layers and forming a first silicide layer for connecting at least a part of a surface of a drain or source region formed in a planar semiconductor layer. | 10-25-2012 |
20120299068 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer. | 11-29-2012 |
20130062673 | SOLID-STATE IMAGING DEVICE - In a solid-state imaging device, a pixel has a first island-shaped semiconductor (P | 03-14-2013 |
20130069149 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes the steps of forming first and second pillar-shaped semiconductors on a substrate at the same time so as to have the same height; forming a first semiconductor layer by doping a bottom region of the first pillar-shaped semiconductor with a donor or acceptor impurity to connect the first semiconductor layer to the second pillar-shaped semiconductor; forming a circuit element including an upper semiconductor region formed by doping an upper region of the first pillar-shaped semiconductor with a donor or acceptor impurity; forming a first conductor layer in the second pillar-shaped semiconductor; forming first and second contact holes that are respectively connected to the first and second pillar-shaped semiconductors; and forming a wiring metal layer that is connected to the upper semiconductor region and the first conductor layer through the first and second contact holes, respectively. | 03-21-2013 |
20130095625 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate. | 04-18-2013 |
20130113037 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact. | 05-09-2013 |
20130140627 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes. | 06-06-2013 |
20130146964 | METHOD OF PRODUCING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes the steps of forming a planar silicon layer, first and second pillar-shaped silicon layers on a silicon substrate; forming a gate insulating film, depositing a metal film and a polysilicon around the gate insulating film, conducting planarization, conducting etching to expose upper portions of the first and second pillar-shaped silicon layers, forming first and second insulating film sidewalls, and forming first and second gate electrodes and a gate line; forming n-type diffusion layers in upper and lower portions of the first pillar-shaped silicon layer, and forming p-type diffusion layers in upper and lower portions of the second pillar-shaped silicon layer; forming a third insulating film sidewall on side walls of the first and second insulating film sidewalls, the first and second gate electrodes, and the gate line; and forming a silicide. | 06-13-2013 |
20130153989 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes. | 06-20-2013 |
20130214334 | SOLID-STATE IMAGING DEVICE - There is provided a solid-state imaging device in which a plurality of pixels is two-dimensionally arranged in a pixel region. Each of the pixels is formed in an island-shaped semiconductor. In this island-shaped semiconductor, a signal line N | 08-22-2013 |
20130228869 | SEMICONDUCTOR DEVICE - An SGT-based static memory cell which is a six-transistor SRAM cell includes an SGT driver transistor including a first gate electrode surrounding a first gate insulating film and composed of at least a metal; an SGT selection transistor including a second gate electrode surrounding a second gate insulating film and composed of at least a metal; an SGT load transistor including a third gate electrode surrounding a third gate insulating film and composed of at least a metal; and a gate wire connected to the second gate electrode. An island-shaped semiconductor layer of the driver transistor has a peripheral length that is less than twice that of an island-shaped semiconductor layer of the selection transistor. A voltage applied to the second gate electrode is lower than a voltage applied to a first-conductivity-type high-concentration semiconductor layer on the upper part of the island-shaped semiconductor layer of the selection transistor. | 09-05-2013 |
20130252413 | SURROUND GATE CMOS SEMICONDUCTOR DEVICE - The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer. | 09-26-2013 |
20130273703 | SEMICONDUCTOR DEVICE INCLUDING A MOS TRANSISTOR AND PRODUCTION METHOD THEREFOR - It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; a bottom doped region formed in contact with a lower part of the semiconductor pillar; a first gate formed around a sidewall of the semiconductor pillar through a first dielectric film therebetween; and a top doped region formed so as to at least partially overlap a top surface of the semiconductor pillar, wherein the top doped region has a top surface having an area greater than that of the top surface of the semiconductor pillar. | 10-17-2013 |
20130307037 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a step of forming a first insulating film around a fin-shaped silicon layer and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer; a step of implanting an impurity into upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer to form diffusion layers; and a step of forming a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad. The polysilicon gate electrode and the polysilicon gate pad have a larger width than the polysilicon gate line. After these steps follow a step of depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and the polysilicon gate line, and depositing a metal layer to form a metal gate electrode and a metal gate line, and a step of forming a contact. | 11-21-2013 |
20130307057 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first pillar-shaped silicon layer formed on a planar silicon layer, a gate insulating film formed around the first pillar-shaped silicon layer, a first gate electrode formed around the gate insulating film, a gate line connected to the first gate electrode, a first first-conductivity-type diffusion layer formed in an upper portion of the first pillar-shaped silicon layer, a second first-conductivity-type diffusion layer formed in a lower portion of the first pillar-shaped silicon layer and an upper portion of the planar silicon layer, a first sidewall having a laminated structure of an insulating film and polysilicon and being formed on an upper sidewall of the first pillar-shaped silicon layer and an upper portion of the first gate electrode, and a first contact formed on the first first-conductivity-type diffusion layer and the first sidewall. | 11-21-2013 |
20130307083 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first planar silicon layer, first and second pillar-shaped silicon layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped silicon layer and a center of the second pillar-shaped silicon layer. | 11-21-2013 |
20130328138 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a first step including forming a planar silicon layer and forming first and second pillar-shaped silicon layers; a second step including forming a gate insulating film around each of the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, the thickness of the polysilicon film being smaller than half of a distance between the first and second pillar-shaped silicon layers, forming a third resist, and forming a gate line; and a third step including depositing a fourth resist so that a portion of the polysilicon film on an upper side wall of each of the first and second pillar-shaped silicon layers is exposed, removing the exposed portion of the polysilicon film, removing the fourth resist, and removing the metal film to form first and second gate electrodes. | 12-12-2013 |
20130341707 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first pillar, a second pillar underneath the first pillar, and a third pillar on a top of the first pillar. The second pillar has a second-conductive type region in a surface thereof except at least a part of a contact surface region with the first pillar, and a first-conductive type region therein and surrounded by the second-conductive type region. The third pillar has a second-conductive type region in a surface thereof except at least a part of a contact surface region with the first pillar, and a first-conductive type region therein and surrounded by the second-conductive type region. The first-conductive type region of each of the second pillar and the third pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type region of a respective one of the second pillar and the third pillar. | 12-26-2013 |
20140016403 | SEMICONDUCTOR MEMORY DEVICE - In a loadless 4T-SRAM constituted using vertical-type transistor SGTs, a small SRAM cell area is realized. In a static memory cell constituted using four MOS transistors, the MOS transistors are SGTs formed on a bulk substrate in which the drains, gates, and sources are arranged in the vertical direction. The gates of access transistors are shared, as a word line, among a plurality of cells adjacent to one another in the horizontal direction. One contact for the word line is formed for each group of cells, thereby realizing a CMOS-type loadless 4T-SRAM with a very small memory cell area. | 01-16-2014 |
20140021525 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped floating gate arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the floating gate and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the floating gate in such a manner that an inter-polysilicon insulating film is interposed between the control gate and the floating gate. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the upper, lower, and inner side surfaces of the control gate. | 01-23-2014 |
20140021588 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD - The object to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit is achieved by forming an inverter which comprises: a first transistor including; an first island-shaped semiconductor layer; a first gate insulating film; a gate electrode; a first first-conductive-type high-concentration semiconductor layer arranged above the first island-shaped semiconductor layer; and a second first-conductive-type high-concentration semiconductor layer arranged below the first island-shaped semiconductor layer, and a second transistor including; a second gate insulating film surrounding a part of the periphery of the gate electrode; a second semiconductor layer in contact with a part of the periphery of the second gate insulating film; a first second-conductive-type high-concentration semiconductor layer arranged above the second semiconductor layer; and a second second-conductive-type high-concentration semiconductor layer arranged below the second semiconductor layer. | 01-23-2014 |
20140042504 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact. | 02-13-2014 |
20140042526 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A SGT-production method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer, where the pillar-shaped silicon layer has the same width as the fin-shaped silicon layer, forming a gate insulating film around the pillar-shaped silicon layer, forming, around the gate insulating film, a metal film and a polysilicon film thinner than the width of the pillar-shaped silicon layer, forming a third resist for forming a gate line, performing anisotropic etching to form the gate line, depositing a fourth resist, exposing the polysilicon film on a sidewall of an upper portion of the pillar-shaped silicon layer, removing the exposed polysilicon film by etching, removing the fourth resist, removing the metal film by etching, and forming a gate electrode connecting to the gate line. | 02-13-2014 |
20140054681 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes. | 02-27-2014 |
20140070298 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device includes a pillar-shaped silicon layer including a first diffusion layer, a channel region, and a second diffusion layer formed in that order from the silicon substrate side, floating gates respectively disposed in two symmetrical directions so as to sandwich the pillar-shaped silicon layer, and a control gate line disposed in two symmetrical directions other than the two directions so as to sandwich the pillar-shaped silicon layer. A tunnel insulating film is formed between the pillar-shaped silicon layer and each of the floating gates. The control gate line is disposed so as to surround the floating gates and the pillar-shaped silicon layer with an inter-polysilicon insulating film interposed therebetween. | 03-13-2014 |
20140070326 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes. | 03-13-2014 |
20140091372 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second oxide film on the planar silicon layer, the second oxide film being thicker than a gate insulating film; and a third step includes forming the gate insulating film around each of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a metal film and a polysilicon film around the gate insulating film, the polysilicon film having a thickness that is smaller than one half a distance between the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a third resist for forming a gate line, and performing anisotropic etching to form the gate line. | 04-03-2014 |
20140091385 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first pillar-shaped silicon layer formed on a planar silicon layer, a gate insulating film formed around the first pillar-shaped silicon layer, a first gate electrode formed around the gate insulating film, a gate line connected to the first gate electrode, a first first-conductivity-type diffusion layer formed in an upper portion of the first pillar-shaped silicon layer, a second first-conductivity-type diffusion layer formed in a lower portion of the first pillar-shaped silicon layer and an upper portion of the planar silicon layer, a first sidewall having a laminated structure of an insulating film and polysilicon and being formed on an upper sidewall of the first pillar-shaped silicon layer and an upper portion of the first gate electrode, and a first contact formed on the first first-conductivity-type diffusion layer and the first sidewall. | 04-03-2014 |
20140091403 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a step of forming a first insulating film around a fin-shaped silicon layer and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer; a step of implanting an impurity into upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer to form diffusion layers; and a step of forming a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad. The polysilicon gate electrode and the polysilicon gate pad have a larger width than the polysilicon gate line. After these steps follow a step of depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and the polysilicon gate line, and depositing a metal layer to form a metal gate electrode and a metal gate line, and a step of forming a contact. | 04-03-2014 |
20140097494 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes forming a fin-shaped silicon layer, a first insulating film around the fin-shaped silicon layer, a pillar-shaped silicon layer on the fin-shaped silicon layer, a gate electrode and a gate insulating film around the pillar-shaped silicon layer, a gate line connected to the gate electrode, a first diffusion layer in an upper portion of the pillar-shaped silicon layer, a second diffusion layer in a lower portion of the pillar-shaped silicon layer and an upper portion of the fin-shaped silicon layer, and a first silicide and a second silicide on the first diffusion layer and the second diffusion layer; an interlayer insulating film to expose an upper portion of the pillar-shaped silicon layer; etching the interlayer insulating film to form a contact hole; depositing a metal to form the first contact on the second silicide; and performing etching to form the metal wire. | 04-10-2014 |
20140097500 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer. | 04-10-2014 |
20140103408 | SOLID-STATE IMAGING DEVICE - In a solid-state imaging device, N regions serving as photoelectric conversion diodes are formed on outer peripheries of P regions in upper portions of island-shaped semiconductors formed on a substrate, and P | 04-17-2014 |
20140117431 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped charge storage layer arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the charge storage layer and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the charge storage layer in such a manner that an insulating film is interposed between the control gate and the charge storage layer. The insulating film is arranged so as to be interposed between the charge storage layer and the upper, lower, and inner side surfaces of the control gate. | 05-01-2014 |
20140131791 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a first step of forming a fin-shaped silicon layer on a silicon substrate using a first resist and forming a first insulating film therearound; and a second step of forming a second insulating film around the fin-shaped silicon layer and etching the second insulating film so as to be left on a side wall of the fin-shaped silicon layer, depositing a third insulating film on the first and second insulating films and the fin-shaped silicon layer, depositing a polysilicon thereon, planarizing a surface thereof, and etching back the polysilicon to expose the third insulating film, forming a second resist, etching the second and third insulating films and then etching the fin-shaped silicon layer and the polysilicon, and removing the second insulating film to form a pillar-shaped silicon layer and a dummy gate formed of the polysilicon. | 05-15-2014 |
20140131810 | SEMICONDUCTOR MEMORY DEVICE - To realize a small SRAM cell area in a loadless 4T-SRAM constituted using vertical-type transistor SGTs. | 05-15-2014 |
20140151767 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a step of forming a first insulating film around a fin-shaped silicon layer and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer; a step of implanting an impurity into upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer to form diffusion layers; and a step of forming a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad. The polysilicon gate electrode and the polysilicon gate pad have a larger width than the polysilicon gate line. After these steps follow a step of depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and the polysilicon gate line, and depositing a metal layer to form a metal gate electrode and a metal gate line, and a step of forming a contact. | 06-05-2014 |
20140203353 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer, a first insulating film around the fin-shaped semiconductor layer, and a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer. A second step forms a gate insulating film around the pillar-shaped semiconductor layer, a gate electrode around the gate insulating film, and a gate line. A third step forms a first first-conductivity-type diffusion layer in an upper portion of the pillar-shaped semiconductor layer and a second first-conductivity-type diffusion layer in a lower portion of the pillar-shaped semiconductor layer and an upper portion of the fin-shaped semiconductor layer. A fourth step includes depositing, planarizing, and etching-back a first interlayer insulating film to expose an upper portion of the pillar-shaped semiconductor layer, depositing a first metal, and etching the metal to form a first sidewall around the upper portion of the pillar-shaped semiconductor layer. | 07-24-2014 |
20140209998 | SEMICONDUCTOR DEVICE - A semiconductor device includes a pillar-shaped semiconductor having an impurity concentration of 10 | 07-31-2014 |
20140213025 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes. | 07-31-2014 |
20140242766 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact. | 08-28-2014 |
20140264560 | SEMICONDUCTOR DEVICE - A SGT-production method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer, where the pillar-shaped silicon layer has the same width as the fin-shaped silicon layer, forming a gate insulating film around the pillar-shaped silicon layer, forming, around the gate insulating film, a metal film and a polysilicon film thinner than the width of the pillar-shaped silicon layer, forming a third resist for forming a gate line, performing anisotropic etching to form the gate line, depositing a fourth resist, exposing the polysilicon film on a sidewall of an upper portion of the pillar-shaped silicon layer, removing the exposed polysilicon film by etching, removing the fourth resist, removing the metal film by etching, and forming a gate electrode connecting to the gate line. | 09-18-2014 |
20140264561 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first fin-shaped silicon layer on a substrate and a second fin-shaped silicon layer on the substrate, each corresponding to the dimensions of a sidewall pattern around a dummy pattern. A silicide in upper portions of n-type and p-type diffusion layers in the upper portions of the first and second fin-shaped silicon layers. A metal gate line is connected to first and second metal gate electrodes and extends in a direction perpendicular to the first fin-shaped silicon layer and the second fin-shaped silicon layer. A first contact is in direct contact with the n-type diffusion layer in the upper portion of the first pillar-shaped silicon layer, and a second contact is in direct contact with the p-type diffusion layer in the upper portion of the second pillar-shaped silicon layer. | 09-18-2014 |
20140339627 | SEMICONDUCTOR DEVICE - A semiconductor device includes a pillar-shaped silicon layer and a first-conductivity-type diffusion layer in an upper portion of the pillar-shaped silicon layer. A sidewall having a laminated structure including an insulating film and polysilicon resides on an upper sidewall of the pillar-shaped silicon layer. A top of the polysilicon of the sidewall is electrically connected to a top of the first-conductivity-type diffusion layer and has the same conductivity as the diffusion layer. | 11-20-2014 |
20140339628 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped silicon layer on a silicon substrate and a first insulating film around the fin-shaped silicon layer. A pillar-shaped silicon layer resides on the fin-shaped silicon layer. A gate electrode and gate insulating film surround the pillar-shaped silicon layer and a gate line is connected to the gate electrode and extends in a direction orthogonally intersecting the fin-shaped silicon layer. A first diffusion layer resides in an upper portion of the pillar-shaped silicon layer and a second diffusion layer resides in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer. A first silicide resides in an upper portion of the first diffusion layer and a second silicide resides in an upper portion of the second diffusion layer. A contact and metal wire are on the second silicide, and a metal wire is on the first contact. | 11-20-2014 |
20140361383 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped silicon layer and a pillar-shaped silicon layer on the fin-shaped silicon layer, where a width of the pillar-shaped silicon layer is equal to a width of the fin-shaped silicon layer. Diffusion layers reside in upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and in a lower portion of the pillar-shaped silicon layer to form. A gate insulating film and a metal gate electrode are around the pillar-shaped silicon layer and a metal gate line extends in a direction perpendicular to the fin-shaped silicon layer and is connected to the metal gate electrode. A contact resides on the metal gate line and a nitride film is on an entire top surface of the metal gate electrode and the metal gate line, except for the bottom of the contact. | 12-11-2014 |
20140374845 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped silicon layer on a semiconductor substrate and extending in a first direction and a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped silicon layer resides on the fin-shaped silicon layer. A width of the pillar-shaped semiconductor layer, perpendicular to the first direction is equal to a width of the fin-shaped semiconductor layer perpendicular to the first direction. A gate insulating film is around the pillar-shaped semiconductor layer and a metal gate electrode is around the gate insulating film. A metal gate line extends in a second direction perpendicular to the first direction of the fin-shaped semiconductor layer and is connected to the metal gate electrode. A metal gate pad is connected to the metal gate line, where the width of the metal gate electrode and the width of the metal gate pad are larger than the width of the metal gate line. | 12-25-2014 |
20150017767 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE HAVING SGTS - In a method for producing a semiconductor device, Si pillars that include i-layers, N | 01-15-2015 |
20150048443 | SEMICONDUCTOR DEVICE - A semiconductor device includes a pillar-shaped silicon layer and a first-conductivity-type diffusion layer in an upper portion of the pillar-shaped silicon layer. A sidewall having a laminated structure including an insulating film and polysilicon resides on an upper sidewall of the pillar-shaped silicon layer. A top of the polysilicon of the sidewall is electrically connected to a top of the first-conductivity-type diffusion layer and has the same conductivity as the diffusion layer. | 02-19-2015 |