Patent application number | Description | Published |
20090006895 | Method for debugging reconfigurable architectures - A method is described for debugging reconfigurable hardware. In one example embodiment, debugging information is written for each configuration cycle into a memory which is then evaluated by a debugger. | 01-01-2009 |
20090031104 | Low Latency Massive Parallel Data Processing Device - Data processing device comprising a multidimensional array of ALUs, having at least two dimensions where the number of ALUs in the dimension is greater or equal to 2, adapted to process data without register caused latency between at least some of the ALUs in the corresponding array. | 01-29-2009 |
20090146691 | LOGIC CELL ARRAY AND BUS SYSTEM - A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points. | 06-11-2009 |
20100153654 | DATA PROCESSING METHOD AND DEVICE - In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory. | 06-17-2010 |
20100281235 | RECONFIGURABLE FLOATING-POINT AND BIT-LEVEL DATA PROCESSING UNIT - Blocks of fixed-point units in a reconfigurable data processing unit assist the efficient calculation of floating decimal point numbers by virtue of joint hardware functions permanently implemented within the block. | 11-04-2010 |
20110119657 | USING FUNCTION CALLS AS COMPILER DIRECTIVES - A method for passing compiler directives into a compiler wherein empty function calls are defined, which call no function, but define compiler directives by its name, is suggested. Thus, by allowing empty functions calls and by handling them automatically, in particular in the automated way suggested, significant improvements over the prior art can be obtained. | 05-19-2011 |
20120017066 | LOW LATENCY MASSIVE PARALLEL DATA PROCESSING DEVICE - Data processing device comprising a multidimensional array of ALUs, having at least two dimension where the number of ALUs in the dimension is greater or equal to 2, adapted to process data without register caused latency between at least some of the ALUs in the corresponding array. | 01-19-2012 |
20120072699 | LOGIC CELL ARRAY AND BUS SYSTEM - A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points. | 03-22-2012 |
20120284630 | Window Proxy - A preferably secured server, hosting a website, connected to the internet, interacting with a user's local machine by means of executing supplemental code in the form of a browser plug-in, with the intent of modifying the capabilities of a conventional internet browser beyond its initially designed capacity, thus relieving the web designer of the limitations imposed by the original browser source code. The browser plug-in executes a process that is run in conjunction with the browser application, enabling the viewer application/process of the present invention to broadcast unrestricted code and UI elements from the local computer's operating system, and presenting the user with robust, interactive applications, framed within the current browsing application window, thus streamlining the user's experience, and providing the appearance of a secure web application, despite the reality that the browser is merely framing the complex application within the browser. | 11-08-2012 |
20120311301 | PIPELINE CONFIGURATION PROTOCOL AND CONFIGURATION UNIT COMMUNICATION - In a method of synchronizing data processing of processor arrangement, responsive to reaching, during execution of a program, a barrier included in a program sequence, the processor arrangement halts the program execution until it is determined that all instructions preceding the barrier in the program sequence have been successfully scheduled for execution. | 12-06-2012 |
20130111188 | LOW LATENCY MASSIVE PARALLEL DATA PROCESSING DEVICE | 05-02-2013 |
20140297948 | METHOD FOR PROCESSING DATA - A method for operating a system on a chip comprising a conventional processor unit (CISC, RISC, VLIW, DSP) and an array processor having a multidimensional arrangement of arithmetic units. Operation information for the array processor are stored in a memory shared between the conventional processor and the array processor. At runtime the conventional processor points the array processor to the memory area comprising the operation information. A management unit inside the array processor is autonomously loading the operation information into the array processor | 10-02-2014 |
20140310466 | Multi-processor bus and cache interconnection system - A multi-processor cache and bus interconnection system. A multi-processor is provided a segmented cache and an interconnection system for connecting the processors to the cache segments. An interface unit communicates to external devices using module IDs and timestamps. A buffer protocol includes a retransmission buffer and method. | 10-16-2014 |
20140325175 | PIPELINE CONFIGURATION PROTOCOL AND CONFIGURATION UNIT COMMUNICATION - The present invention includes an integrated module including a plurality of data processing units including a memory device having processing instruction data stored therein. The processing instruction data including subconfiguration data for at least one of the data processing units, the subconfiguration data including a plurality of blocks. The integrated module further includes a barrier disposed between a first block and a second block of the plurality of blocks. Wherein, the data processing units process the processing instruction data from the memory device such that the barrier provides for the data processing units to observe a configuration sequence of the subconfiguration data. | 10-30-2014 |
20140331194 | Method for manufacturing a chip from a system definition - A method for manufacturing a chip from a system definition, the system definition describing a plurality of cells, buses and external I/O. The cell definitions are defined by providing two libraries, a first containing a superset of cell definitions; and a second a plurality of HDL definitions of cells selected from the first library. The method further included creating the system definition from the second library, a bus definition, and an external I/O definition. | 11-06-2014 |
20140359254 | Logical cell array and bus system - A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points. | 12-04-2014 |
20150026431 | Method of Processing Data with an Array of Data Processors According to Application ID - A method wherein a plurality of data processors are associated with application IDs whereby the array processes a plurality of applications in parallel. | 01-22-2015 |
20150033000 | Parallel Processing Array of Arithmetic Unit having a Barrier Instruction - A parallel processing array processor has a plurality of arithmetic units and a unit that manages barrier instructions whereby processing of program sequences may be coordinated. The array processor further comprises a hierarchy of assigned units whereby multiple program sequences may be processed in parallel. | 01-29-2015 |