Patent application number | Description | Published |
20080212577 | CHIP CIRCUIT FOR COMBINED AND DATA COMPRESSED FIFO ARBITRATION FOR A NON-BLOCKING SWITCH - A system for switching data packets through a multiple (m) input, multiple (n) output switching device providing switching having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped. | 09-04-2008 |
20120159132 | Accelerating Data Packet Parsing - Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle. | 06-21-2012 |
20120300642 | Accelerating Data Packet Parsing - Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle. | 11-29-2012 |
20130311697 | SWITCHING DEVICE FOR ROUTING DATA, COMUTER INTERCONNECTION NETWORK AND ROUTING METHOD USING SUCH DEVICE - The invention is directed to a switching device (S | 11-21-2013 |
20160085722 | DATA PACKET PROCESSING - Proposed is an action machine for processing packet data in a network processor. The action machine comprises: first and second data storage units adapted to store data for processing; and a processing unit adapted to process data from the first and second data storage units. The first storage unit is adapted to be accessed by the processing unit and a unit external to the action machine, and the second storage unit is adapted to only be accessed by the processing unit. | 03-24-2016 |
20160105267 | ASSEMBLING RESPONSE PACKETS - Proposed is an action machine for assembling response packets in a network processor. The action machine comprises: a first register array adapted to store data for entry into fixed-length fields of differing response packets, a fixed-length field having the same length in the differing response packets; and a second register array adapted to store data for entry into variable-length fields of differing response packets, a variable-length field having different values or lengths in the differing response packets. The action machine is adapted to assemble a response packet by combining data stored in the first register array with data stored in the second register array. | 04-14-2016 |
20160134529 | NETWORK CONTROLLER-SIDEBAND INTERFACE PORT CONTROLLER - Aspects of the present disclosure are directed towards a network interface controller that could provide a connection for a device to a network. The network interface controller can include a sideband port controller. The sideband port controller can provide a sideband connection between the network and a sideband endpoint circuit that can be operative to communicate with the network via a sideband. The sideband port controller can include an event notification unit operative to compile information into an event notification packet. The sideband port controller can further include a packet parser. In embodiments, the packet parser could be operative to analyses a packet to provide an indication that the packet contains the event notification packet. In embodiments, the sideband port controller could be operative to forward the information in the event notification packet to the sideband endpoint circuit, responsive to that indication. | 05-12-2016 |
20160134549 | STICKY AND TRANSIENT MARKERS FOR A PACKET PARSER - A packet parser has a set of marker elements each comprising a one bit latch and connected to store flag values from the results of the application of parser rules. Some marker elements are connected to provide the stored marker values as input to the parser rule logic to be taken into account in the processing of subsequent parser rules and some are connected to control external hardware. Some markers are reset at the end of each packet. A special toggle marker element toggles its value when its address is selected and other marker elements are connected to store, when its own address is selected, the value of the toggle element. Other markers toggle their own value when selected. | 05-12-2016 |
20160134559 | NETWORK CONTROLLER-SIDEBAND INTERFACE PORT CONTROLLER - Aspects of the present disclosure are directed towards a network interface controller that could provide a connection for a device to a network. The network interface controller can include a sideband port controller. The sideband port controller can provide a sideband connection between the network and a sideband endpoint circuit that can be operative to communicate with the network via a sideband. The sideband port controller can include an event notification unit operative to compile information into an event notification packet. The sideband port controller can further include a packet parser. In embodiments, the packet parser could be operative to analyses a packet to provide an indication that the packet contains the event notification packet. In embodiments, the sideband port controller could be operative to forward the information in the event notification packet to the sideband endpoint circuit, responsive to that indication. | 05-12-2016 |