Patent application number | Description | Published |
20100277622 | Image sensor including noise removing unit, image pickup device having the image sensor, and image sensing method performed in the image sensor - An image sensor including a noise removing unit may sense images accurately by measuring the amount of noise generated when the image sensor does not perform a sensing operation, storing information about the measured noise amount in each pixel, and removing photocharge corresponding to the information about the measured noise amount during image sensing. | 11-04-2010 |
20110128430 | Image Sensors Having Multiple Photoelectric Conversion Devices Therein - Image sensors include a second photoelectric conversion device disposed in a lower portion of a substrate and a first photoelectric conversion device extending between the secondary photoelectric conversion device and a light receiving surface of the substrate. Electrical isolation between the first and second photoelectric conversion devices is provided by a photoelectron barrier, which may be an optically transparent electrically insulating material. MOS transistors may be utilized to transfer photoelectrons generated within the first and second photoelectric conversion devices to a floating diffusion region within the image sensor. These transistors may represent one example of means for transferring photoelectrons generated in the first and second photoelectric conversion devices to a floating diffusion region in the substrate, in response to first and second gating signals, respectively. The first and second gating signals may be active during non-overlapping time intervals. | 06-02-2011 |
20140267859 | IMAGE SENSOR, OPERATING METHOD THEREOF, AND DEVICE INCLUDING THE IMAGE SENSOR - An image sensor includes a first photoelectric conversion element supplying charges to a first charge storage node, a first charge storage element adjusting an amount of charges supplied from a charge supply source to the first charge storage node in response to a feedback signal, and a feedback signal generating circuit generating the feedback signal based on an amount of charges in the first charge storage node. | 09-18-2014 |
Patent application number | Description | Published |
20080263336 | Processor Having Efficient Function Estimate Instructions - High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic. | 10-23-2008 |
20080297506 | Ray Tracing with Depth Buffered Display - An image is generated that includes ray traced pixel data and rasterized pixel data. A synergistic processing unit (SPU) uses a rendering algorithm to generate ray traced data for objects that require high-quality image rendering. The ray traced data is fragmented, whereby each fragment includes a ray traced pixel depth value and a ray traced pixel color value. A rasterizer compares ray traced pixel depth values to corresponding rasterized pixel depth values, and overwrites ray traced pixel data with rasterized pixel data when the corresponding rasterized fragment is “closer” to a viewing point, which results in composite data. A display subsystem uses the resultant composite data to generate an image on a user's display. | 12-04-2008 |
20120143932 | Data Structure For Tiling And Packetizing A Sparse Matrix - A computer system retrieves a slice of sparse matrix data, which includes multiple rows that each includes multiple elements. The computer system identifies one or more non-zero values stored in one or more of the rows. Each identified non-zero value corresponds to a different row, and also corresponds to an element location within the corresponding row. In turn, the computer system stores each of the identified non-zero values and corresponding element locations within a packet at predefined fields corresponding to the different rows. | 06-07-2012 |
20120144130 | Optimizing Output Vector Data Generation Using A Formatted Matrix Data Structure - A computer system retrieves a packet that includes non-zero elements that correspond to sparse-matrix rows. Within the packet, the non-zero elements are stored in predefined fields that each correspond to one of the sparse-matrix rows. The computer system computes output values to correspond with each of the sparse-matrix rows using the non-zero elements and corresponding input values. In turn, the computer system stores the computed output values in consecutive locations within an output buffer and processes the output values accordingly. | 06-07-2012 |
20120203985 | Data Structure For Tiling And Packetizing A Sparse Matrix - A computer system retrieves a slice of sparse matrix data, which includes multiple rows that each includes multiple elements. The computer system identifies one or more non-zero values stored in one or more of the rows. Each identified non-zero value corresponds to a different row, and also corresponds to an element location within the corresponding row. In turn, the computer system stores each of the identified non-zero values and corresponding element locations within a packet at predefined fields corresponding to the different rows. | 08-09-2012 |
20120210081 | Optimizing Output Vector Data Generation Using A Formatted Matrix Data Structure - A computer system retrieves a packet that includes non-zero elements that correspond to sparse-matrix rows. Within the packet, the non-zero elements are stored in predefined fields that each correspond to one of the sparse-matrix rows. The computer system computes output values to correspond with each of the sparse-matrix rows using the non-zero elements and corresponding input values. In turn, the computer system stores the computed output values in consecutive locations within an output buffer and processes the output values accordingly. | 08-16-2012 |
Patent application number | Description | Published |
20090157219 | Intelligent Sleeve Container for Use in a Controlled Syringe System - Various embodiments of the present invention concern improving the dosing accuracy and efficacy of systems that calculate medicine doses for injection in animals and prepare the correct dose in an automated syringe subsystem. In an embodiment, the improvement is gained by simultaneously protecting the medicine from ambient outdoor temperatures that thermally degrade its efficacy while precisely monitoring the amount of medicine remaining inside the source vial to prevent inadvertent under-dosing due to undetected source depletion. This dual-sleeve system (one for temperature, one for data storage concerning the source vial contents) forms an intelligent adjunct to current and future automated injection technology used to maintain healthy livestock. | 06-18-2009 |
20110110920 | METHOD OF TREATING PERIPHERAL ARTERIAL DISEASE - An agonist of a non-proteolytically activated thrombin receptor can be used in a method for treating peripheral arterial disease. The agonist can be a thrombin peptide derivative. In some embodiments, the peripheral arterial disease is characterized by intermittent claudication. The thrombin peptide derivatives to be used in the methods can have amino acid sequences similar to a region of thrombin. Usually, the thrombin peptide derivatives are 12-23 amino acid residues in length. In some cases, the thrombin peptide derivatives are dimers, and in particular, dimers that result from formation of a disulfide bond between two cysteine residues of peptide monomers. | 05-12-2011 |
20110117075 | THROMBIN DERIVED PEPTIDES FOR SMOOTH MUSCLE RELAXATION - Agonists of a non-proteolytically activated thrombin receptor, and more particularly, thrombin peptide derivatives, can be used in methods to cause smooth muscle relaxation. Compositions comprising thrombin peptide derivatives can be administered to a subject with a disease or disorder that can be ameliorated by relaxation of smooth muscle. Such compositions can also be administered to a subject to facilitate medical, diagnostic or surgical procedures. | 05-19-2011 |
20130130978 | METHOD OF TREATING ENDOTHELIAL DYSFUNCTION - Endothelial dysfunction (ED) is associated with a number of diseases and disorders. Agonists of the non-proteolytically activated thrombin receptor can be used in methods to treat ED or ED-related diseases and disorders. | 05-23-2013 |
Patent application number | Description | Published |
20080197868 | CIRCUIT BOARD TESTING DEVICE WITH SELF ALIGNING PLATES - A circuit board tester and method that precisely aligns the probe plate and circuit board is disclosed. With a circuit board and probe plate mounting within a housing having a top and bottom, hinged together, at closure there may be slight misalignments of the two. By making one of the two plates floating, or laterally slideable with respect to each other, it is possible to make final alignment at closure. One of the two plates can be provided with a pin and the other with a pin receiving alignment block. With the lateral sideability, the pin and block can insure proper probe alignment. Additional systems for correcting misaligned pins or blocks are also disclosed. | 08-21-2008 |
20100019793 | CIRCUIT BOARD TESTING DEVICE WITH SELF ALIGNING PLATES - A circuit board tester and method that precisely aligns the probe plate and circuit board is disclosed. With a circuit board and probe plate mounting within a housing having a top and bottom, hinged together, at closure there may be slight misalignments of the two. By making one of the two plates floating, or laterally slideable with respect to each other, it is possible to make final alignment at closure. One of the two plates can be provided with a pin and the other with a pin receiving alignment block. With the lateral sideability, the pin and block can insure proper probe alignment. Additional systems for correcting misaligned pins or blocks are also disclosed. | 01-28-2010 |
20110234248 | CIRCUIT BOARD TESTING DEVICE WITH SELF ALIGNING PLATES - A circuit board tester and method that precisely aligns the probe plate and circuit board is disclosed. With a circuit board and probe plate mounting within a housing having a top and bottom, hinged together, at closure there may be slight misalignments of the two. By making one of the two plates floating, or laterally slideable with respect to each other, it is possible to make final alignment at closure. One of the two plates can be provided with a pin and the other with a pin receiving alignment block. With the lateral sideability, the pin and block can insure proper probe alignment. Additional systems for correcting misaligned pins or blocks are also disclosed. | 09-29-2011 |
Patent application number | Description | Published |
20080250415 | Priority based throttling for power/performance Quality of Service - A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the effect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces. | 10-09-2008 |
20120239875 | APPARATUS AND METHOD FOR HETEROGENEOUS CHIP MULTIPROCESSORS VIA RESOURCE ALLOCATION AND RESTRICTION - A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed. | 09-20-2012 |
20120246407 | METHOD AND SYSTEM TO IMPROVE UNALIGNED CACHE MEMORY ACCESSES - A method and system to improve unaligned cache memory accesses. In one embodiment of the invention, a processing unit has logic to facilitate access of at least two cache memory lines of a cache memory in a single read operation. By doing so, it avoids additional read operations or cycles to read the required data that is cached in more than one cache memory line. Embodiments of the invention facilitate the streaming of unaligned vector loads that does not require substantially more power than streaming aligned vector loads. For example, in one embodiment of the invention, the streaming of unaligned vector loads consumes less than two times the power requirements of streaming aligned vector loads. | 09-27-2012 |
20130173893 | HARDWARE COMPILATION AND/OR TRANSLATION WITH FAULT DETECTION AND ROLL BACK FUNCTIONALITY - Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes the programs into a second language including instructions to support processor features not encoded into the original language encoding of the programs. In one embodiment, an execution unit executes instructions of the second language including an operation-check instruction to perform a first operation and record the first operation result for a comparison, and an operation-test instruction to perform a second operation and a fault detection operation by comparing the second operation result to the recorded first operation result. In some embodiments, an execution unit executes instructions of the second language including commit instructions to record execution checkpoint states of registers mapped to architectural registers, and roll-back instructions to restore the registers mapped to architectural registers to previously recorded execution checkpoint states. | 07-04-2013 |
20140189413 | DISTRIBUTED POWER MANAGEMENT FOR MULTI-CORE PROCESSORS - A system and method for performing distributed power control in a processor comprising an array of cores enables each core to regulate power at least partially independently. Global power management settings are made accessible to all cores and communication between cores propagates power consumption information between nearest neighbors in the array. Each core attempts to best regulate its own power consumption in accordance with global power consumption information and/or specific instructions from a global power manager. In this manner local opportunistic load balancing may be achieved in a scalable manner suitable for a large array of cores. | 07-03-2014 |
20150046910 | HARDWARE COMPILATION AND/OR TRANSLATION WITH FAULT DETECTION AND ROLL BACK FUNCTIONALITY - Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes the programs into a second language including instructions to support processor features not encoded into the original language encoding of the programs. In one embodiment, an execution unit executes instructions of the second language including an operation-check instruction to perform a first operation and record the first operation result for a comparison, and an operation-test instruction to perform a second operation and a fault detection operation by comparing the second operation result to the recorded first operation result. In some embodiments, an execution unit executes instructions of the second language including commit instructions to record execution checkpoint states of registers mapped to architectural registers, and roll-back instructions to restore the registers mapped to architectural registers to previously recorded execution checkpoint states. | 02-12-2015 |