Patent application number | Description | Published |
20090096509 | Bandgap Reference Circuits for Providing Accurate Sub-1V Voltages - A reference voltage circuit includes a first PMOS device having a first source, a first gate, and a first drain, wherein the first source is coupled to a power supply node; and a second PMOS device having a second source, a second gate and, a second drain. The second source is coupled to the power supply node. The first and the second PMOS devices have constant source-drain currents. The reference voltage circuit further includes a third PMOS device having a third source, a third gate, and a third drain; and a resistor coupled between the third drain and the ground. The third source is coupled to the power supply node. The first, the second, and the third gates are interconnected. The first, the second, and the third drains are virtually interconnected. | 04-16-2009 |
20100164766 | DAC Variation-Tracking Calibration - A method of calibrating a digital-to-analog converter (DAC) is provided. The DAC includes a least-significant bit (LSB) block, and dummy LSB block adjacent to the LSB block. The DAC has a most-significant bit (MSB) block, which includes MSB thermometer macros. The method includes measuring the dummy LSB block to obtain a dummy LSB sum; and calibrating the MSB block so that each of the MSB thermometer macros provides a substantially same current as the dummy LSB sum. | 07-01-2010 |
20110012763 | Background Calibration of Analog-to-Digital Converters - A method of operating an analog-to-digital converter (ADC) includes providing the ADC including a plurality of stages, each including an operational amplifier, and a first capacitor and a second capacitor including a first input end and a second input end, respectively. Each of the first capacitor and the second capacitor includes an additional end connected to a same input of the operational amplifier. The method further includes performing a plurality of signal conversions. Each of the signal conversions includes, in an amplifying phase of one of the plurality of stages, applying a first voltage to the first input end of the one of the plurality of stages, randomly selecting a second voltage from two different voltages; and applying the second voltage to the second input end of the one of the plurality of stages. | 01-20-2011 |
20110037631 | DAC CALIBRATION - Mechanisms to calibrate a digital to analog converter (DAC) of an SDM (sigma delta modulator) are disclosed. An extra DAC element in addition to the DAC is used to function in place of a DAC element under calibration. A signal (e.g., a random sequence of −1 and +1) is injected to the DAC element under calibration, and the estimated error and compensation are acquired. | 02-17-2011 |
20110037632 | ADC CALIBRATION - An analog to digital convertor (ADC) includes a plurality of comparators one of which is referred to as an auxiliary comparator (e.g., comparator “Aux”). This comparator Aux is calibrated in the background while other comparators function as usual. Once having been calibrated, the comparator Aux replaces a first comparator, which becomes a new comparator Aux, is calibrated, and replaces the second comparator. This second comparator becomes the new comparator Aux, is calibrated, and replaces the third comparator, etc., until all comparators are calibrated. In effect, at any one point in time, a comparator may be calibrated as desire while other comparators and thus the ADC are operating as usual. | 02-17-2011 |
20120075132 | METHOD AND APPARATUS FOR CALIBRATING SIGMA-DELTA MODULATOR - In a method of converting an analog signal to digital format, an analog input signal is received and processed using sigma-delta modulation to provide a first digital signal that represents the analog input signal in digital format and to provide a second digital signal that represents a first error introduced during the sigma-delta modulation. A second error that is error introduced during the sigma-delta modulation is estimated. A pre-correction signal is determined based on the first and second digital signals. A difference between the estimated second error and the pre-correction digital signal is determined to provide a digital output signal representing the analog input signal in digital format. An error correction element operable to adjust the digital output signal based on the analog input signal, the digital output signal, and the second digital signal is controlled. | 03-29-2012 |
20120081244 | METHOD AND APPARATUS FOR ANALOG TO DIGITAL CONVERSION - An analog to digital converter (ADC) comprises an input node having a variable analog input voltage, first and second switched capacitor circuits, an operational amplifier, and a control circuit. The first switched capacitor circuit has first and second capacitors and is coupled to the input node, and the second switched capacitor circuit has third and fourth capacitors and is coupled to the input node. The operational amplifier is configured to be conditionally coupled to only one of the first and second switched capacitor circuits at a time and configured to conditionally provide feedback to the switched capacitor circuits via an output node. The control circuit is coupled to the first and second switched capacitor circuits for conditional coupling to the operational amplifier. | 04-05-2012 |
20120133536 | DAC CALIBRATION - Mechanisms to calibrate a digital to analog converter (DAC) of an SDM (sigma delta modulator) are disclosed. An extra DAC element in addition to the DAC is used to function in place of a DAC element under calibration. A signal (e.g., a random sequence of −1 and +1) is injected to the DAC element under calibration, and the estimated error and compensation are acquired. | 05-31-2012 |
20120212359 | ADC Calibration Apparatus - An analog-to-digital (ADC) calibration apparatus comprises a calibration buffer, a comparator and a digital calibration block. Each reference voltage is sent to a track-and-hold amplifier as well as the calibration buffer. The comparator compares the output from the track-and-hold amplifier and the output from the calibration buffer and generates a binary number. Based upon a successive approximation method, the digital calibration block finds a correction voltage for ADC offset and nonlinearity compensation. By employing the ADC calibration apparatus, each reference voltage can be calibrated and the corresponding correction voltage can be used to modify the reference voltage during an ADC process. | 08-23-2012 |
20120249351 | ADC CALIBRATION - An analog-to-digital converter (ADC) including a plurality of comparators connected to the ADC. The ADC further includes a first pair of terminals and a second pair of terminals connected to each of the plurality of comparators. The ADC further includes a first pair of switches coupled to each of the first pair of terminals and a second pair of switches coupled to each of the second pair of terminals, where the first and second pair of switches are configured to alternate a corresponding comparator between normal operation and a calibration configuration. Comparators other than the corresponding comparator are configured for normal operation if the corresponding comparator is configured to be calibrated. | 10-04-2012 |
20130015876 | APPARATUS AND METHOD FOR MEASURING DEGRADATION OF CMOS VLSI ELEMENTSAANM LAI; Fang-Shi JordanAACI Chia YiAACO TWAAGP LAI; Fang-Shi Jordan Chia Yi TWAANM LU; Chih-ChengAACI Tainan CityAACO TWAAGP LU; Chih-Cheng Tainan City TWAANM LIN; Yung-FuAACI Hsinchu CityAACO TWAAGP LIN; Yung-Fu Hsinchu City TWAANM HSUEH; Hsu-FengAACI Tainan CityAACO TWAAGP HSUEH; Hsu-Feng Tainan City TWAANM CHANG; Chin-HaoAACI Hsinchu CityAACO TWAAGP CHANG; Chin-Hao Hsinchu City TWAANM WENG; Cheng YenAACI Hsinchu CityAACO TWAAGP WENG; Cheng Yen Hsinchu City TWAANM MHALA; Manoj M.AACI HsinchuAACO TWAAGP MHALA; Manoj M. Hsinchu TW - The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages. | 01-17-2013 |
20130141260 | PIPELINE ANALOG-TO-DIGITAL CONVERTER - A pipelined ADC includes a first, second, and third pairs of comparators. The first pair of comparators compare an input voltage to a first positive reference voltage and to a first negative reference voltage. The second pair of comparators compare the input voltage to a second positive reference voltage and to a second negative reference voltage. Each comparator of the first and second pairs of comparators outputs a digital signal to an encoder. A third pair of comparators compares the input voltage to a third positive reference voltage and to a third negative reference voltage, and a comparator compares the input voltage to ground. The comparator and each comparator of the third pair of comparators is configured to output respective digital signals to an encoder. A multiplying digital-to-analog converter outputs a voltage based on the input voltage, an output from the encoder, and an output of the random number generator. | 06-06-2013 |