Patent application number | Description | Published |
20090055681 | INTRA-DISK CODING SCHEME FOR DATA-STORAGE SYSTEMS - Exemplary embodiments of the present invention comprise a method for the use of an intra-disk redundancy storage protection operation for the scrubbing of a disk. The method comprises initiating a disk scrubbing operation upon each disk of a plurality of disks that are comprised within a storage disk array, issuing a disk scrubbing command for a predetermined segment of the disks that are comprised within the storage disk array at a predetermined time interval, and identifying an unrecoverable segment on a disk. The method further comprises determining if unrecoverable sectors comprised within the unrecoverable segment can be reconstructed, and reconstructing the unrecoverable sectors of the unrecoverable segment and relocating the segment to a spare storage location on the disk in the event that the segment cannot be reconstructed within its original storage location. | 02-26-2009 |
20090080107 | METHOD OF CONTROLLING MOVEMENTS OF A POSITION OF A MICROSCANNER - The invention relates to a method of controlling movements of a positioner of a micro-scanner, the method comprising: determining the vibration resonance frequency ranges of the positioner, and performing a main scan by a controlled movement of the positioner. | 03-26-2009 |
20090174964 | SERVO CHANNEL FOR TAPE DRIVE SYSTEMS - Provided are techniques for synchronous servo channel for a data tape drive. A servo reader is configured to read servo bursts from a data tape. An anti-aliasing filter is operable to output a bandlimited signal and is coupled to receive a servo channel signal comprising servo bursts from the servo reader. An analog-to-digital converter (ADC) is operable to output signal samples and is coupled to receive the bandlimited signal from the anti-aliasing filter. An interpolation and control unit is operable to output interpolated signal samples and control signals, has a first input coupled to receive the signal samples from the ADC, and has a second input coupled to receive the correlation signal samples from the dibit correlator. A dibit correlator is operable to output correlation signal samples and is coupled to receive the interpolated signal samples and control signals from the interpolation and control unit. | 07-09-2009 |
20090237832 | ERROR CORRECTION CODING OF LONGITUDINAL POSITION INFORMATION - A sequential data storage medium, comprising a sequence of plurality of servo patterns that provide lateral position information and longitudinal position information, wherein each of the plurality of servo patterns comprises a first burst comprising a first plurality of pulses, a second burst comprising a second plurality of pulses, a third burst comprising a third plurality of pulses, and a fourth burst comprising a fourth plurality of pulses. The spacings between the first plurality of pulses, in combination with the spacings between the second plurality of pulses, encode a first bit without affecting the recovery of lateral position information. The spacings between the third plurality of pulses, in combination with the spacings between the fourth plurality of pulses, encode a second bit without affecting the recovery of lateral position information. The sequence of plurality of servo patterns comprises a sequence of the first bits and a sequence of the second bits to form an error-correction codeword providing error-correction capability. | 09-24-2009 |
20090279201 | JOINT SPECIFICATION OF SERVO FORMAT AND SERVO READER PARAMETERS FOR TAPE DRIVE SYSTEMS - A servo pattern, including stripes arranged in servo bursts for use in position error signal (PES) generation, is provided in which a stripe width is narrower than 1.7 μm and in which the stripes are oriented at an azimuth angle which in absolute value is equal to or larger than 6 degrees. | 11-12-2009 |
20090279202 | HEAD DESIGN FOR WRITING SERVO PATTERNS ON MAGNETIC TAPE - A servo write head is provided and is configured to simultaneously write at least two servo patterns in respective servo bands on linear magnetic tape. Centerlines of the servo patterns are substantially uniformly spaced in the lateral direction. In addition, the servo patterns of all adjacent respective servo bands are displaced relative to each other in a longitudinal direction by an amount that is related to a length of a servo frame and a type of the servo patterns. | 11-12-2009 |
20100001772 | METHODS AND SYSTEMS FOR DELAY COMPENSATION IN GLOBAL PLL-BASED TIMING RECOVERY LOOPS - A system in one embodiment includes a global PLL circuit comprising multiple inputs, each input being for receiving an error signal associated with an individual channel; and a delay compensation circuit coupled to the global PLL circuit. A method in one embodiment includes receiving multiple error signals, each error signal being associated with an individual channel; applying one or more delay compensation signals to the error signals; and outputting phase error output signals for each of the channels. | 01-07-2010 |
20100214688 | DUAL ACTUATOR FOR A READ-WRITE DATA STORAGE DEVICE - A data storage device includes a first head module independently moveably mounted relative to the storage device. The first head module includes at least one of a read element and a write element. In addition, the data storage device includes a second head module independently moveably mounted relative to the storage device. The second head module includes at least one of a read element and a write element operatively associated with the at least one of a read element and write element of the first head module. The second head module is selectively shiftable relative to the first head module in order to align the at least one of the read element and the write element of the first head module and the at least one of the read element and the write element of the second head module to one another. | 08-26-2010 |
20100214690 | ROLLER GUIDE FOR MAGNETIC TAPE WITH MULTIPLE GUIDING SECTIONS - A device for guiding a magnetic tape in a data storage drive including a cylindrical body rotatable about a longitudinal axis. The cylindrical body having opposing ends and defining a surface area for mating with a magnetic tape. A curved section at opposite ends of the cylindrical body is contiguous with the surface area of the cylindrical body. A plurality of vents in the cylindrical body allow air flow therethrough between the surface area and the tape. The amount of air flow between the cylindrical body and the tape produces varying frictional forces on the tape such that the tape is biased to a nominal position on the cylindrical body by air pressure on the tape resulting from the air flow interaction with the curved sections. | 08-26-2010 |
20100232047 | DATA INTERLEAVING IN TAPE DRIVES - Methods and apparatus for interleaving data in a multitrack tape drive and for writing data on a multitrack tape in the tape drive. One method includes: partitioning the data into m(2 | 09-16-2010 |
20110010434 | STORAGE SYSTEM - A pseudo peer-to-peer network system including several clients, each adapted to execute a path driver program. A path driver program is provided, including the steps of locating storage peers connected to the network via a network interface for storing or accessing data items provided in memories of storage peers by means of a global address table. The global address table is updated periodically by at least one configuration server of the pseudo peer-to-peer network. The network further includes at least one time server, which generates a global time clock to which local time clocks of all storage peers of the pseudo peer-to-peer network are synchronized such that a global address table updated by the configuration server is activated by all storage peers at the same scheduled time to be consistent throughout the pseudo peer-to-peer network at all times. | 01-13-2011 |
20110029715 | WRITE-ERASE ENDURANCE LIFETIME OF MEMORY STORAGE DEVICES - A memory management system and method for managing memory blocks of a memory device of a computer. The system includes a free block data structure including free memory blocks for writing, and sorting the free memory blocks in a predetermined order based on block write-erase endurance cycle count and receiving new user-write requests to update existing data and relocation write requests to relocate existing data separately, a user-write block pool for receiving youngest blocks holding user-write data (i.e., any page being updated frequently) from the free block data structure, a relocation block pool for receiving oldest blocks holding relocation data (i.e., any page being updated infrequently) from the free block data structure, and a garbage collection pool structure for selecting at least one of user-write blocks and relocation blocks for garbage collection, wherein the selected block is moved back to the free block data structure upon being relocated and erased. | 02-03-2011 |
20110102934 | CANCELLATION OF TIME-VARYING PERIODIC DISTURBANCES IN SERVO CONTROL SYSTEMS - Various embodiments for addressing time-varying periodic disturbances in a servo control system are provided. Each of a plurality of coefficients is updated based on an estimation of at least one disturbance frequency. The updated plurality of coefficients is provided to at least one peak filter modifying an input signal of the servo control system. The peak filter is operable in view of the updated plurality of coefficients to cancel at least one of the time-varying periodic disturbances. | 05-05-2011 |
20110131369 | LOGIC DEVICE - A logic device for communicating with a memory package with a first protocol, communicating with a memory controller with a second protocol, and for performing a protocol conversion between the first and the second protocol. | 06-02-2011 |
20110131472 | SOLID-STATE STORAGE SYSTEM WITH PARALLEL ACCESS OF MULTIPLE FLASH/PCM DEVICES - Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random/burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random/burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional/operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I/O performance in terms of maximum achievable read/write data rate. | 06-02-2011 |
20110134562 | OPERATING A REEL-TO-REEL SYSTEM - A method for operating a reel-to-reel system of a storage device with a first reel, a second reel, a first motor and a second motor, the first motor drives the first reel and the second motor drives the second reel. The system transports a tape supplied by one of the two reels and taken up by the other reel. A tape velocity and tape tension between the first and reels, and a longitudinal displacement are determined. An estimated state vector depends on the tape velocity, tape tension and longitudinal displacement. A reference state vector depends on a predetermined reference tape velocity and a predetermined reference tape tension. A first control signal and a second control signal are generated dependent on the estimated state vector and the reference state vector. The first motor is controlled by the first control signal and the second motor is controlled by the second control signal. | 06-09-2011 |
20110145475 | REDUCING ACCESS CONTENTION IN FLASH-BASED MEMORY SYSTEMS - Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full. | 06-16-2011 |
20110176237 | MAGNETIC TAPE SERVO FORMAT ALLOWING FOR INCREASED LINEAR TAPE DENSITY AND SYSTEMS THEREOF - According to one embodiment, a magnetic recording tape includes a plurality of servo tracks, each servo track comprising a series of magnetically defined bars having an average height of between about 80 microns and about 120 microns, wherein an average stripe angle of the bars is between about 10° and about 25°. A stripe angle is measured between a longitudinal axis of each respective bar and a line oriented perpendicular to a direction of tape travel and parallel to a plane of the tape, wherein an average stripe width of the bars is between about 1.0 micron and about 2.2 microns and an average servo frame length of groups of the bars comprising a servo frame is between about 120 microns and about 180 microns. In more embodiments, a servo format and a system including a servo format are disclosed, along with other embodiments of magnetic tapes. | 07-21-2011 |
20110200090 | METHOD FOR AN EQUALIZER COMPUTATION IN A MEDIA SYSTEM USING A DATA SET SEPARATOR SEQUENCE - An equalizer coefficients generator receives a DSS sequence and a DSS readback sequence, which is a function of a channel processing of the DSS sequence by a read channel. The generator generates a coefficient cyclic equalizer vector as a function of the DSS sequence and the DSS readback sequence. The generator further generates an error signal as a function of a comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector. An unacceptable error signal indicates a need to adjust the coefficient cyclic equalizer vector to yield an acceptable comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector. | 08-18-2011 |
20110202708 | Integrating A Flash Cache Into Large Storage Systems - An I/O enclosure module is provided with one or more I/O enclosures having a plurality of slots for receiving electronic devices. A host adapter is connected a first slot of the I/O enclosure module and is configured to connect a host to the I/O enclosure. A device adapter is connected to a second slot of the I/O enclosure module and is configured to connect a storage device to the I/O enclosure module. A flash cache is connected to a third slot of the I/O enclosure module and includes a flash-based memory configured to cache data associated with data requests handled through the I/O enclosure module. A primary processor complex manages data requests handled through the I/O enclosure module by communicating with the host adapter, device adapter, and flash cache to manage to the data requests. | 08-18-2011 |
20110242692 | DATA-DEPENDENT NOISE-PREDICTIVE MAXIMUM LIKELIHOOD DETECTION (DD-NPML) FOR MAGNETIC RECORDING - In one embodiment, a method includes applying one or more whitening filters to an input stream of digitized samples from a magnetic data channel to produce a filtered sequence, performing one or more branch metric calculations to the filtered sequence to produce a branch metric, and applying a multi-state data-dependent noise-predictive maximum likelihood (DD-NPML) detector to the branch metric to produce an output stream. In another embodiment, a multi-channel data storage system includes a head for reading data from a storage medium, logic for applying one or more whitening filters to an input stream of digitized samples from a magnetic data channel to produce a filtered sequence, logic for performing one or more branch metric calculations to the filtered sequence to produce a branch metric, and logic for applying a multi-state DD-NPML detector to the branch metric to produce an output stream. Other systems and methods are described as well. | 10-06-2011 |
20110242884 | Programming at Least One Multi-Level Phase Change Memory Cell - A method of applying at least one programming pulse to the a PCM cell for programming the PCM cell to have a respective definite cell state, the definite cell state being defined by a definite resistance level using an annealing pulse or a melting pulse. The respective definite cell state represents two information entities, a step of applying a first reading pulse to the respective programmed PCM cell to provide a first resistance value, a step of applying at least a second reading pulse to the respective programmed PCM cell to provide a second resistance value, the first reading pulse and the second reading pulse being different pulses; and a step of determining the respective definite cell state of the respective programmed PCM cell dependent on the respective provided first resistance value and the respective provided second resistance value. | 10-06-2011 |
20110246821 | RELIABILITY SCHEME USING HYBRID SSD/HDD REPLICATION WITH LOG STRUCTURED MANAGEMENT - In one embodiment, a method of storing data includes storing a first copy of data in a solid state memory and storing a second copy of the data in a hard disk drive memory substantially simultaneously with the storing the first copy. In another embodiment, a system for storing data includes a solid state memory, at least one hard disk drive memory, and a controller for controlling storage of data in the solid state memory and the hard disk drive memory. Other methods, systems, and computer program products are also described according to various embodiments. | 10-06-2011 |
20110246864 | DATA DEPENDENT NPML DETECTION AND SYSTEMS THEREOF - According to one embodiment, a data detection system includes a coefficient-and-variance engine for selecting which infinite impulse response (IIR) filter and prediction error variance to process and store at any time, and a maximum-likelihood sequence detector. The coefficient-and-variance engine comprises a filter bank storing a plurality of IIR filters that represent a plurality of data-dependent noise whitening or noise prediction filters; a least-mean square (LMS) engine for adapting each IIR filter to actual noise conditions: a variance hank storing a plurality of prediction error variance values; and a data-dependent prediction error variance computation unit which updates the plurality of prediction error variance values. The maximum-likelihood sequence detector includes a metric computation unit that employs the plurality of IIR filters in the filter bank and the plurality of prediction error variances in the variance bank to adaptively compute detector branch metrics. Other systems and methods are also described in other embodiments. | 10-06-2011 |
20110296085 | CACHE MEMORY MANAGEMENT IN A FLASH CACHE ARCHITECTURE - Provided are a system, method, and computer program product for managing cache memory to cache data units in at least one storage device. A cache controller is coupled to at least two flash bricks, each comprising a flash memory. Metadata indicates a mapping of the data units to the flash bricks caching the data units, wherein the metadata is used to determine the flash bricks on which the cache controller caches received data units. The metadata is updated to indicate the flash brick having the flash memory on which data units are cached. | 12-01-2011 |
20120001142 | CARBON-BASED MEMORY ELEMENT - One embodiment of the disclosure can provide a storage layer of a resistive memory element comprising a resistance changeable material. The resistance changeable material can include carbon. Contact layers can be provided for contacting the storage layer. The storage layer can be disposed between a bottom contact layer and a top contact layer. The resistance changeable material can be annealed at a predetermined temperature over a predetermined annealing time for rearranging an atomic order of the resistance changeable material. | 01-05-2012 |
20120166749 | DATA MANAGEMENT IN SOLID-STATE STORAGE DEVICES AND TIERED STORAGE SYSTEMS - A method for managing data in a data storage system having a solid-state storage device and alternative storage includes identifying data to be moved in the solid-state storage device for internal management of the solid-state storage; moving at least some of the identified data to the alternative storage instead of the solid-state storage; and maintaining metadata indicating the location of data in the solid-state storage device and the alternative storage. | 06-28-2012 |
20120200955 | USING A READ-WRITE DATA STORAGE DEVICE HAVING A DUAL ACTUATOR - A method of aligning read elements and write elements with a storage media in a data storage device includes determining a position of a data track associated with the storage media, shifting one of a first and second head module relative to the storage media. The first head module includes at least one of a read element and a write element and the second head module includes at least one of a read element and a write element operatively associated with the at least one of the read element and write element of the first head module. The first head module is selectively shiftable relative to the second head module. The method further includes aligning one of the at least one read element and write element of the one of the first and second head module that is shifted with the data track on the storage media. | 08-09-2012 |
20120260150 | DATA MANAGEMENT IN SOLID STATE STORAGE SYSTEMS - Methods and apparatus are provided for controlling data management operations including storage of data in solid state storage of a solid state storage system. Input data is stored in successive groups of data write locations in the solid state storage. Each group comprises a set of write locations in each of a plurality of logical subdivisions of the solid state storage. The input data to be stored in each group is encoded in accordance with first and second linear error correction codes. The encoding is performed by constructing from the input data to be stored in each group a logical array of rows and columns of data symbols. The rows and columns are respectively encoded in accordance with the first and second linear error correction codes to produce an encoded array in which all rows correspond to respective first codewords and columns correspond to respective second codewords. | 10-11-2012 |
20120266050 | Data Management in Solid State Storage Devices - A mechanism is provided for controlling a solid state storage device in which the solid state storage comprises erasable blocks each comprising a plurality of data write locations. Input data is stored in successive groups of data write locations, each group comprising write locations in a set of erasable blocks in each of a plurality of logical subdivisions of the solid state storage. The input data is error correction encoded such that each group contains an error correction code for the input data in that group. Metadata, indicating the location of input data in the solid state storage, is maintained in memory, An indication of validity of data stored in each data write location is also maintained, Prior to erasing a block, valid input data is recovered from the or each said group containing write locations in that block. The recovered data is then re-stored as new input data. | 10-18-2012 |
20120278544 | FLASH MEMORY CONTROLLER - A Flash memory controller is coupled to a first Flash memory package through a first Flash memory interface and to a second Flash memory package through the first Flash memory interface. The Flash memory controller is designed to receive a first instruction relating to the first Flash memory package and to perform a first process depending on the first instruction. The Flash memory controller is further designed to receive a second instruction relating to the second Flash memory package and to perform a second process depending on the second instruction. The Flash memory controller is further adapted for splitting the first process into at least two first sub-steps and for splitting the second process into at least two second sub-steps. The Flash memory controller is further adapted for executing the first and second sub-steps, and for interleaving execution of first and second sub-steps. | 11-01-2012 |
20120290779 | DATA MANAGEMENT IN SOLID-STATE STORAGE DEVICES AND TIERED STORAGE SYSTEMS - A method for managing data in a data storage system having a solid-state storage device and alternative storage includes identifying data to be moved in the solid-state storage device for internal management of the solid-state storage; moving at least some of the identified data to the alternative storage instead of the solid-state storage; and maintaining metadata indicating the location of data in the solid-state storage device and the alternative storage. | 11-15-2012 |
20120293889 | METHOD AND APPARATUS FOR OPERATING A STORAGE DEVICE - Method for operating a storage device with a tape and a head wherein the head comprises a first and a second read element. Each read element is operable to detect servo-pattern of a particular servo band. The first and the second read element are arranged such that the tape at first passes one of both read elements and subsequently passes the other of both read elements when the tape moves in a predetermined longitudinal direction. A tape transport direction of the tape along the longitudinal direction is determined. The first read element is selected dependent on the determined tape transport direction, when the determined tape transport direction represents a direction where the tape at first passes the first read element and subsequently the second read element. Otherwise the second read element is selected. A position error signal is determined dependent on the selected read element. | 11-22-2012 |
20120297128 | REDUCING ACCESS CONTENTION IN FLASH-BASED MEMORY SYSTEMS - Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full. | 11-22-2012 |
20120303919 | WRITE-ERASE ENDURANCE LIFETIME OF MEMORY STORAGE DEVICES - A memory management system and method for managing memory blocks of a memory device of a computer. The system includes a free block data structure including free memory blocks for writing, and sorting the free memory blocks in a predetermined order based on block write-erase endurance cycle count and receiving new user-write requests to update existing data and relocation write requests to relocate existing data separately, a user-write block pool for receiving youngest blocks holding user-write data (i.e., any page being updated frequently) from the free block data structure, a relocation block pool for receiving oldest blocks holding relocation data (i.e., any page being updated infrequently) from the free block data structure, and a garbage collection pool structure for selecting at least one of user-write blocks and relocation blocks for garbage collection, wherein the selected block is moved back to the free block data structure upon being relocated and erased. | 11-29-2012 |
20130013974 | DATA ENCODING IN SOLID STATE STORAGE DEVICES - Methods and apparatus are provided for encoding input data for recording in s-level storage of a solid state storage device, where s f 2. Input data words are encoded in groups of M input data words in accordance with first and second BCH codes to produce, for each group, a set of M first codewords of the first BCH code. The set of M first codewords is produced such that at least one predetermined linear combination of the M first codewords produces a second codeword of the second BCH code, this second BCH code being a sub-code of the first BCH code. The sets of M first codewords are then recorded in the s-level storage. If each of the first and second codewords comprises N q-ary symbols where q=p | 01-10-2013 |
20130013980 | Data Management in Solid State Storage Devices - A mechanism is provided for controlling a solid state storage device in which the solid state storage comprises erasable blocks each comprising a plurality of data write locations. Input data is stored in successive groups of data write locations, each group comprising write locations in a set of erasable blocks in each of a plurality of logical subdivisions of the solid state storage. The input data is error correction encoded such that each group contains an error correction code for the input data in that group. Metadata, indicating the location of input data in the solid state storage, is maintained in memory. An indication of validity of data stored in each data write location is also maintained. Prior to erasing a block, valid input data is recovered from the or each said group containing write locations in that block. The recovered data is then re-stored as new input data. | 01-10-2013 |
20130021845 | PROGRAMMING AT LEAST ONE MULTI-LEVEL PHASE CHANGE MEMORY CELL - A method is provided that comprises a step of programming the PCM cell to have a respective definite cell state by at least one current pulse flowing to the PCM cell, said respective definite cell state being defined at least by a respective definite resistance level, a step of controlling said respective current pulse by a respective bitline pulse and a respective wordline pulse, and a step of controlling said respective bitline pulse and said respective wordline pulse dependent on an actual resistance value of the PCM cell and a respective reference resistance value being defined for the definite resistance level. | 01-24-2013 |
20130044540 | PROGRAMMING AT LEAST ONE MULTI-LEVEL PHASE CHANGE MEMORY CELL - An apparatus for programming at least one multi-level Phase Change Memory (PCM) cell having a first terminal and a second terminal A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling the at least one current pulse by applying a respective first pulse to the first terminal and a respective second pulse applied to the second terminal of the PCM cell. The respective cell state is defined by a respective resistance level. The control device receives a reference resistance value defining a target resistance level for the cell, and further receives an actual resistance value of said PCM cell such that the applying the respective first pulse and said respective second pulse is based on said actual resistance value of the PCM cell and said received reference resistance value. | 02-21-2013 |
20130046930 | OPTIMIZING LOCATIONS OF DATA ACCESSED BY CLIENT APPLICATIONS INTERACTING WITH A STORAGE SYSTEM - A method for optimizing locations of physical data accessed by one or more client applications interacting with a storage system, with the storage system comprising at least two redundancy groups having physical memory spaces and data bands. Each of the data bands corresponds to physical data stored on several of the physical memory spaces. A virtualized logical address space includes client data addresses utilizable by the one or more client applications. A storage controller is configured to map the client data addresses onto the data bands, such that a mapping is obtained, wherein the one or more client applications can access physical data corresponding to the data bands. | 02-21-2013 |
20130046931 | OPTIMIZING LOCATIONS OF DATA ACCESSED BY CLIENT APPLICATIONS INTERACTING WITH A STORAGE SYSTEM - A method for optimizing locations of physical data accessed by one or more client applications interacting with a storage system, with the storage system comprising at least two redundancy groups having physical memory spaces and data bands. Each of the data bands corresponds to physical data stored on several of the physical memory spaces. A virtualized logical address space includes client data addresses utilizable by the one or more client applications. A storage controller is configured to map the client data addresses onto the data bands, such that a mapping is obtained, wherein the one or more client applications can access physical data corresponding to the data bands. | 02-21-2013 |
20130111106 | PROMOTION OF PARTIAL DATA SEGMENTS IN FLASH CACHE | 05-02-2013 |
20130111131 | DYNAMICALLY ADJUSTED THRESHOLD FOR POPULATION OF SECONDARY CACHE | 05-02-2013 |
20130111133 | DYNAMICALLY ADJUSTED THRESHOLD FOR POPULATION OF SECONDARY CACHE | 05-02-2013 |
20130111134 | MANAGEMENT OF PARTIAL DATA SEGMENTS IN DUAL CACHE SYSTEMS | 05-02-2013 |
20130111146 | SELECTIVE POPULATION OF SECONDARY CACHE EMPLOYING HEAT METRICS | 05-02-2013 |
20130111160 | SELECTIVE SPACE RECLAMATION OF DATA STORAGE MEMORY EMPLOYING HEAT AND RELOCATION METRICS | 05-02-2013 |
20130145089 | CACHE MEMORY MANAGEMENT IN A FLASH CACHE ARCHITECTURE - Provided is a method for managing cache memory to cache data units in at least one storage device. A cache controller is coupled to at least two flash bricks, each comprising a flash memory. Metadata indicates a mapping of the data units to the flash bricks caching the data units, wherein the metadata is used to determine the flash bricks on which the cache controller caches received data units. The metadata is updated to indicate the flash brick having the flash memory on which data units are cached. | 06-06-2013 |
20130166827 | WEAR-LEVEL OF CELLS/PAGES/SUB-PAGES/BLOCKS OF A MEMORY - The invention is directed to a method for wear-leveling cells or pages or sub-pages or blocks of a memory such as a flash memory, the method comprising:—receiving (S | 06-27-2013 |
20130185512 | MANAGEMENT OF PARTIAL DATA SEGMENTS IN DUAL CACHE SYSTEMS - For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache. Unrequested data of the whole data segment is split and positioned at a Least Recently Used (LRU) portion of the demotion queue of the higher level of cache. The unrequested data is pinned in place until a write of the whole data segment to the lower level of cache completes. | 07-18-2013 |
20130205077 | PROMOTION OF PARTIAL DATA SEGMENTS IN FLASH CACHE - For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, the temporal bits and sequential bits are transferred from the primary storage to the secondary storage. The temporal bits are allowed to age on the secondary storage. | 08-08-2013 |
20130214239 | METHOD FOR MANUFACTORING A CARBON-BASED MEMORY ELEMENT AND MEMORY ELEMENT - A method for manufacturing a resistive memory element includes providing a storage layer comprising a resistance changeable material, said resistance changeable material comprising carbon; providing contact layers for contacting the storage layer, wherein the storage layer is disposed between a bottom contact layer and a top contact layer; and doping the resistance changeable material with a dopant material. | 08-22-2013 |
20130222940 | MAGNETIC TAPE SERVO FORMAT ALLOWING FOR INCREASED LINEAR TAPE DENSITY AND SYSTEMS THEREOF - In one general embodiment, a magnetic recording tape includes a plurality of servo tracks, each servo track comprising a series of magnetically defined bars, wherein an average stripe width of the bars is between about 1.0 micron and about 2.2 microns, where an average servo frame length of groups of the bars comprising a servo frame is between about 120 microns and about 180 microns. In another general embodiment, a system includes a head having at least one servo reader and an array of data transducers of a type selected from a group consisting of readers and writers; and a controller operative to selectively enable every other transducer of a particular type in the array in a first mode of operation, and operative to selectively enable every transducer of the particular type in the array in a second mode of operation. | 08-29-2013 |
20130232294 | ADAPTIVE CACHE PROMOTIONS IN A TWO LEVEL CACHING SYSTEM - Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is stored in the second cache. It is determined that the page is to be promoted from the second cache to the first cache. In response to determining that the reference count is greater than zero, the page is added to a Least Recently Used (LRU) end of an LRU list in the first cache. In response to determining that the reference count is less than or equal to zero, the page is added to a Most Recently Used (LRU) end of the LRU list in the first cache. | 09-05-2013 |
20130232295 | ADAPTIVE CACHE PROMOTIONS IN A TWO LEVEL CACHING SYSTEM - Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is stored in the second cache. It is determined that the page is to be promoted from the second cache to the first cache. In response to determining that the reference count is greater than zero, the page is added to a Least Recently Used (LRU) end of an LRU list in the first cache. In response to determining that the reference count is less than or equal to zero, the page is added to a Most Recently Used (LRU) end of the LRU list in the first cache. | 09-05-2013 |
20130346538 | MANAGING CACHE MEMORIES - A method for managing cache memories includes providing a computerized system including a shared data storage system (CS) configured to interact with several local servers that serve applications using respective cache memories, and access data stored in the shared data storage system; providing cache data information from each of the local servers to the shared data storage system, the cache data information comprising cache hit data representative of cache hits of each of the local servers, and cache miss data representative of cache misses of each of the local servers; aggregating, at the shared data storage system, at least part of the cache hit and miss data received and providing the aggregated cache data information to one or more of the local servers; and at the local servers, updating respective one or more cache memories used to serve respective one or more applications based on the aggregated cache data information. | 12-26-2013 |
20140181383 | RELIABILITY SCHEME USING HYBRID SSD/HDD REPLICATION WITH LOG STRUCTURED MANAGEMENT - In one embodiment, a method of managing data includes managing a first copy of data in a solid state memory using a controller of the solid state memory, and managing a second copy of the data in a hard disk drive memory using the controller. In another embodiment, a system for storing data includes a solid state memory, at least one hard disk drive memory, and a controller for controlling storage of data in both the solid state memory and the hard disk drive memory. Other methods, systems, and computer program products are also described according to various embodiments. | 06-26-2014 |
20140201448 | MANAGEMENT OF PARTIAL DATA SEGMENTS IN DUAL CACHE SYSTEMS - For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache. | 07-17-2014 |
20140330817 | TAPE DRIVE SYSTEM SERVER - A tape drive system server includes a non-volatile memory used as a cache memory for storing data files, at least part of the cache memory comprising a first region managed using a First In First Out policy management and a second region managed using a Least Recently Used policy management; a file system interface for interacting with data files stored on a tape drive system; an interface for allowing one or more remote systems reading and writing data stored on the cache memory; the server configured to: receive from the one or more remote systems one or more write requests for writing one or more data files; interpret attributes associated to data files instructed to be written by the one or more remote systems; and store data files instructed to be written by the remote systems according to the interpreted attributes. | 11-06-2014 |
20150036413 | RESISTIVE MEMORY ELEMENT BASED ON OXYGEN-DOPED AMORPHOUS CARBON - The present invention is notably directed to a resistive memory element comprising a resistively switchable material coupled to two conductive electrodes, wherein the resistively switchable material is an amorphous compound comprising carbon and oxygen. Moreover, the carbon and oxygen stoichiometric ratio can be within a range of 1:0.30 to 1:0.80. | 02-05-2015 |
20150052413 | DECODING OF LDPC CODE - It is provided a method for decoding a sequence of bits encoded by a LPDC code. The method comprises providing a set of bit states, including a first state and a second state, and a set of conditions to change a bit state including a first condition 5 and a second condition. The first condition and the second condition are different. The method comprises reading the value of each bit of the sequence, associating each bit to a respective state of the set according to the values as read, determining that an evaluated condition is met and changing the state of the target bit as a result of the condition being met. The method may then set the value of the target bit of the 10 sequence according to the state thereof. Such a method provides a solution for decoding a sequence of bits encoded by a LDPC code with better performance than the classic bit-flipping algorithm with only a slight increase in complexity. | 02-19-2015 |
20150074343 | LOGIC DEVICE - A logic device for communicating with a memory package with a first protocol, communicating with a memory controller with a second protocol, and for performing a protocol conversion between the first and the second protocol. | 03-12-2015 |