Patent application number | Description | Published |
20130193588 | SEMICONDUCTOR PACKAGE - A semiconductor package includes first and second semiconductor elements electrically interconnected by a connection structure. The first and second semiconductor elements are joined by a protection structure that includes an adhesive layer surrounded by a retention layer. | 08-01-2013 |
20130299969 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor chip, a second semiconductor chip and a sealing member. The first semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface and having an opening that extends in a predetermined depth from the second surface, and a plurality of through electrodes extending in a thickness direction from the first surface, end portions of the through electrodes being exposed through a bottom surface of the opening. The second semiconductor chip is received in the opening and mounted on the bottom surface of the opening. The sealing member covers the second semiconductor chip in the opening. | 11-14-2013 |
20130344627 | METHOD OF FABRICATING WAFER LEVEL PACKAGE - A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed. | 12-26-2013 |
20140239478 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first semiconductor chip at least partially overlapping a second semiconductor chip. The first semiconductor chip is coupled to a substrate and has a first width, and the second semiconductor chip has a second width. The device also includes a heat sink coupled to the second semiconductor chip and having a third width different from at least one of the first width or the second width. A package molding section at least partially overlaps a first area of the heat sink and does not overlap a second area of the heat sink which includes a top surface of the heat sink. | 08-28-2014 |
20140239536 | HYDROGEL COMPOSITION FOR A MASK BASE AND METHOD FOR MANUFACTURING A HYDROGEL USING SAME - A hydrogel composition includes 0.1 to 10 wt % of a cross-linking agent, 0.2 to 6 wt % of a gelling polymer, 0.5 to 20 wt % of a polyhydric alcohol, and 70 to 90 wt % of purified water to maintain a form without a supporter, be stable without fluidization even when a hydrogel is immersed in cosmetics or pharmaceuticals, and allow the cosmetics or the pharmaceuticals to be uniformly delivered to skin. | 08-28-2014 |
20140271596 | EMULSIFIED HYDROGEL COMPOSITION AND A PRODUCTION METHOD THEREFOR - The present invention relates to an emulsified hydrogel composition and to a production method therefor, wherein, by incorporating between 20 and 30 percent by weight of a gelling solution and an emulsion obtained by mixing between 45 and 60 percent by weight of an aqueous component and between 15 and 30 percent by weight of an oil component, it is possible to simultaneously provide the skin with an aqueous fraction and an oil fraction, and it is possible to enhance functionality due to the inclusion of a high content of a dermatologically active component dissolved in the oil component. | 09-18-2014 |
20140299980 | SEMICONDUCTOR PACKAGES INCLUDING A HEAT SPREADER AND METHODS OF FORMING THE SAME - Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer. | 10-09-2014 |
20150137345 | SEMICONDUCTOR PACKAGE HAVING HEAT SPREADER - A semiconductor package includes a heat spreader. The semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on the first semiconductor chip. The heat spreader may be formed on the first semiconductor chip. A thermal interfacial material (TIM) layer may be formed to be in contact with the first semiconductor chip and the heat spreader and may cover side surfaces of the second semiconductor chip. Heat generated by the first semiconductor chip may be emitted through the TIM layer and the heat spreader. Thermal stress caused by a difference in coefficients of thermal expansion (CTEs) between the substrate and the first semiconductor chip may be distributed to ensure structural stability. | 05-21-2015 |