Patent application number | Description | Published |
20090114902 | TENSILE STRAINED GE FOR ELECTRONIC AND OPTOELECTRONIC APPLICATIONS - A semiconductor structure is provided. The semiconductor structure includes one or more III-IV material-based semiconductor layers. A tensile-strained Ge layer is formed on the one or more a III-IV material-based semiconductor layers. The tensile-strained Ge layer is produced through lattice-mismatched heteroepitaxy on the one or more a III-IV material-based semiconductor layers. | 05-07-2009 |
20090242935 | MONOLITHICALLY INTEGRATED PHOTODETECTORS - Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based photodetector comprising an active region including at least a portion of the monocrystalline silicon layer. The structure also includes a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon. The structure includes at least one non-silicon photodetector comprising an active region including at least a portion of the second monocrystalline semiconductor layer. | 10-01-2009 |
20100022073 | Method of Fabricating CMOS Inverter and Integrated Circuits Utilizing Strained Silicon Surface Channel MOSFETS - A method of fabricating a circuit comprising an nMOSFET includes providing a substrate, depositing a strain-inducing material comprising germanium over the substrate, and integrating a pMOSFET on the substrate, the pMOSFET comprising a strained channel having a surface roughness of less than 1 nm. The strain-inducing material is proximate to and in contact with the pMOSFET channel, the strain in the pMOSFET channel is induced by the strain-inducing material, and a source and a drain of the pMOSFET are at least partially formed in the strain-inducing material. | 01-28-2010 |
20100116329 | METHODS OF FORMING HIGH-EFFICIENCY SOLAR CELL STRUCTURES - Methods for forming solar cells include forming, over a substrate, a first junction comprising at least one III-V material and having a threading dislocation density of less than approximately 10 | 05-13-2010 |
20100116942 | HIGH-EFFICIENCY SOLAR CELL STRUCTURES - Solar cells include a substrate consisting essentially of silicon, a first junction disposed over the substrate, the first junction comprising at least one III-V material and having a threading dislocation density of less than approximately 10 | 05-13-2010 |
20100206216 | Method of Producing High Quality Relaxed Silicon Germanium Layers - A method for minimizing particle generation during deposition of a graded Si.sub.1-xGe.sub.x layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si.sub.1-xGe.sub.x layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm.sup.2 on the substrate. | 08-19-2010 |
20100221512 | DIGITAL METAMORPHIC ALLOYS FOR GRADED BUFFERS - Digital metamorphic alloy (DMA) buffer structures for transitioning from a bottom crystalline layer to a lattice mismatched top crystalline layer, and methods for manufacturing such layers are described. In some embodiments, a layered crystalline structure includes a first layer of a first crystalline material having a first in-plane lattice constant and a second layer of a second crystalline material disposed over the first layer and having a second in-plane lattice constant that is lattice mismatched with the first crystalline material. Multiple sets of buffer layers may be disposed between the first layer and the second layer. Each set is a digital metamorphic alloy including a buffer layer of a third crystalline material and a buffer layer of a fourth crystalline material where an effective in-plane lattice constant of each set falls between the first lattice of the first layer and the second lattice constant of the second layer. | 09-02-2010 |
20110073908 | III-V Semiconductor Device Structures - The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. | 03-31-2011 |
20110124146 | METHODS OF FORMING HIGH-EFFICIENCY MULTI-JUNCTION SOLAR CELL STRUCTURES - In various embodiments, solar cells include a junction including SiGe, a junction including at least one III-V material, and may be formed on silicon substrates and/or with silicon-based capping layers thereover. | 05-26-2011 |
20110132445 | HIGH-EFFICIENCY MULTI-JUNCTION SOLAR CELL STRUCTURES - In various embodiments, solar cells include a junction including SiGe, a junction including at least one III-V material, and may be formed on silicon substrates and/or with silicon-based capping layers thereover. | 06-09-2011 |
20110143495 | METHODS OF FORMING HIGH-EFFICIENCY MULTI-JUNCTION SOLAR CELL STRUCTURES - In various embodiments, solar cells include a junction including SiGe, a junction including at least one III-V material, and may be formed on silicon substrates and/or with silicon-based capping layers thereover. | 06-16-2011 |
20110177681 | Method of Producing High Quality Relaxed Silicon Germanium Layers - A method for minimizing particle generation during deposition of a graded Si | 07-21-2011 |
20110318893 | METHODS FOR FORMING SEMICONDUCTOR DEVICE STRUCTURES - The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. | 12-29-2011 |
20120125203 | Water purification and enhancement systems - Water purification system comprising filtration media sized with respect to each other to allow a first contaminant in the water to saturate the first medium with a delay prior to saturation of the second medium with a second contaminant. | 05-24-2012 |
20130040433 | Semiconductor Structures Employing Strained Material Layers with Defined Impurity Gradients and Methods for Fabricating Same - Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced. | 02-14-2013 |
20140051230 | Methods for Forming Semiconductor Device Structures - The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. | 02-20-2014 |
20140166066 | HIGH-EFFICIENCY SOLAR-CELL ARRAYS WITH INTEGRATED DEVICES AND METHODS FOR FORMING THEM - In various embodiments, an array of discrete solar cells with associated devices such as bypass diodes is formed over a single substrate. | 06-19-2014 |
20140220755 | Semiconductor Structures Employing Strained Material Layers with Defined Impurity Gradients and Methods for Fabricating Same - Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced. | 08-07-2014 |
20140242778 | Methods of Forming Strained-Semiconductor-on-Insulator Device Structures - The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. | 08-28-2014 |
20140374327 | METHOD AND APPARATUS FOR POINT OF USE WATER FILTRATION - An apparatus for water filtration includes a base a filtration receptacle coupled to the base and a carafe removably coupled to the base. The filtration receptacle includes a water inlet and a water outlet. The filtration receptacle includes a pleated filter positioned between the water inlet and the water outlet. The pleated filter has a pleat face characterized by a surface having a plurality of peaks and a plurality of valleys, such that the surface is disposed in a plurality of planes. The filtration receptacle is structurally configured to maintain the pleated filter in an orientation wherein the pleat face of the pleated filter transverses a water-flow path extending from the water inlet to the water outlet. The filtration receptacle is further configured to induce water-flow along the water-flow path by at least one of a receptacle orientation and a receptacle geometry. The carafe includes an inlet coupled to the water outlet in the filtration receptacle. | 12-25-2014 |