Patent application number | Description | Published |
20100208869 | MEASURING STRAIN OF EPITAXIAL FILMS USING MICRO X-RAY DIFFRACTION FOR IN-LINE METROLOGY - In a method for use of x-ray diffraction to measure the strain on the top silicon germanium layer of an SOI substrate, the location of the peak diffraction area of an upper silicon layer of the SOI substrate is determined by first determining the peak diffraction area of the upper silicon layer on a reference pad (where the SOI thickness is about 700-900 Angstroms) within a die formed on a semiconductor wafer. The x-ray beam then moves to that location on the pad of interest to be measured and begins the XRD scan on the pad of interest to ultimately determine the strain of the top silicon germanium layer of the pad of interest | 08-19-2010 |
20110316046 | Field Effect Transistor Device - A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material. | 12-29-2011 |
20120146050 | MEASUREMENT OF CMOS DEVICE CHANNEL STRAIN BY X-RAY DIFFRACTION - A direct measurement of lattice spacing by X-ray diffraction is performed on a periodic array of unit structures provided on a substrate including semiconductor devices. Each unit structure includes a single crystalline strained material region and at least one stress-generating material region. For example, the single crystalline strained material region may be a structure simulating a channel of a field effect transistor, and the at least one stress-generating material region may be a single crystalline semiconductor region in epitaxial alignment with the single crystalline strained material region. The direct measurement can be performed in-situ at various processing states to provide in-line monitoring of the strain in field effect transistors in actual semiconductor devices. | 06-14-2012 |
20120190216 | ANNEALING TECHNIQUES FOR HIGH PERFORMANCE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE FABRICATION - A semiconductor structure is provided. In some cases, an absorber having a low deposition temperature is applied to at least a portion of the structure. At least a portion of the structure is subjected to a long flash anneal process. | 07-26-2012 |
20130175547 | FIELD EFFECT TRANSISTOR DEVICE - A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material. | 07-11-2013 |
20140080275 | Multigate FinFETs with Epitaxially-Grown Merged Source/Drains - Method of forming multi-gate finFETs with epitaxially-grown merged source/drains. Embodiments of the invention may include forming a plurality of semiconductor fins joined by a plurality of inter-fin semiconductor regions, depositing a sacrificial gate over a center portion of each of the plurality of fins, forming a first merge layer over a first end of each of the plurality of fins to form a first merged fin region, forming a second merge layer over the second end of each of the plurality of fins to form a second merged fin region, etching a portion of the first merged fin region to form a first source/drain base region, etching a portion of the second merged fin region to form a second source/drain base region, forming a first source/drain region on the first source/drain base region, and forming a second source/drain region on the second source/drain base region. | 03-20-2014 |
20140159161 | MEASUREMENT OF CMOS DEVICE CHANNEL STRAIN BY X-RAY DIFFRACTION - A direct measurement of lattice spacing by X-ray diffraction is performed on a periodic array of unit structures provided on a substrate including semiconductor devices. Each unit structure includes a single crystalline strained material region and at least one stress-generating material region. For example, the single crystalline strained material region may be a structure simulating a channel of a field effect transistor, and the at least one stress-generating material region may be a single crystalline semiconductor region in epitaxial alignment with the single crystalline strained material region. The direct measurement can be performed in-situ at various processing states to provide in-line monitoring of the strain in field effect transistors in actual semiconductor devices. | 06-12-2014 |
20140308782 | SELF-LIMITING SELECTIVE EPITAXY PROCESS FOR PREVENTING MERGER OF SEMICONDUCTOR FINS - A self-limiting selective epitaxy process can be employed on a plurality of semiconductor fins such that the sizes of raised active semiconductor regions formed by the selective epitaxy process are limited to dimensions determined by the sizes of the semiconductor fins. Specifically, the self-limiting selective epitaxy process limits growth of the semiconductor material along directions that are perpendicular to crystallographic facets formed during the selective epitaxy process. Once the crystallographic facets become adjoined to one another or to a dielectric surface, growth of the semiconductor material terminates, thereby preventing merger among epitaxially deposited semiconductor materials. | 10-16-2014 |
20150014773 | Partial FIN On Oxide For Improved Electrical Isolation Of Raised Active Regions - A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions. | 01-15-2015 |