Patent application number | Description | Published |
20090164763 | METHOD AND APPARATUS FOR A DOUBLE WIDTH LOAD USING A SINGLE WIDTH LOAD PORT - A single micro-instruction to perform either an N-bit or a 2N-bit load is provided. A microprocessor having an N-bit load port performs either an N-bit load or a 2N-bit load in a single cycle with the same micro-instruction being used for both the N-bit and the 2N-bit load. | 06-25-2009 |
20090300319 | APPARATUS AND METHOD FOR MEMORY STRUCTURE TO HANDLE TWO LOAD OPERATIONS - An apparatus and method to increase memory bandwidth is presented. In one embodiment, the apparatus comprises a load array having: a first array to store a plurality of load operation entries and a second array to store a second plurality of load operation entries. The apparatus further comprises: a store array having a plurality of store operation entries; a first address generation unit coupled to send a linear address of a first load operation to the first array and to send a linear address of a first store operation to the store array; and a second address generation unit coupled to send a linear address of a second load operation to the second array and to send a linear address of a second store operation to the store array. | 12-03-2009 |
20100161907 | POSTING WEAKLY ORDERED TRANSACTIONS - A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system. | 06-24-2010 |
20100169382 | METAPHYSICAL ADDRESS SPACE FOR HOLDING LOSSY METADATA IN HARDWARE - A method and apparatus for metaphysical address space for holding lossy metadata is herein described. An explicit or implicit metadata access operation referencing data address of a data item is encountered. Hardware modifies the data address to a metadata address including a metaphysical extension. The metaphysical extension overlays one or more metaphysical address space(s) on the data address space. A portion of the metadata address including the metaphysical extension is utilized to search a tag array of the cache memory holding the data item. As a result, metadata access operations only hit metadata entries of the cache based on the metadata address extension. However, as the metadata is held within the cache, the metadata potentially competes with data for space within the cache. | 07-01-2010 |
20100169579 | READ AND WRITE MONITORING ATTRIBUTES IN TRANSACTIONAL MEMORY (TM) SYSTEMS - A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item. | 07-01-2010 |
20100169580 | MEMORY MODEL FOR HARDWARE ATTRIBUTES WITHIN A TRANSACTIONAL MEMORY SYSTEM - A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model. | 07-01-2010 |
20120117334 | READ AND WRITE MONITORING ATTRIBUTES IN TRANSACTIONAL MEMORY (TM) SYSTEMS - A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item. | 05-10-2012 |
20120159079 | MEMORY MODEL FOR HARDWARE ATTRIBUTES WITHIN A TRANSACTIONAL MEMORY SYSTEM - A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model. | 06-21-2012 |
20140223226 | APPARATUS AND METHOD FOR DETECTING AND RECOVERING FROM DATA FETCH ERRORS - An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage. | 08-07-2014 |
20140344815 | CONTEXT SWITCHING MECHANISM FOR A PROCESSING CORE HAVING A GENERAL PURPOSE CPU CORE AND A TIGHTLY COUPLED ACCELERATOR - An apparatus is described having multiple cores, each core having: a) an accelerator; and, b) a general purpose CPU coupled to the accelerator. The general purpose CPU has functional unit logic circuitry to execute an instruction that returns an amount of storage space to store context information of the accelerator. | 11-20-2014 |
Patent application number | Description | Published |
20090070236 | Diamond and Precious Stone Trading Platform with Funding and Delivery Transparency - The transparent diamond and precious stone trading platform and method has funding and delivery transparency during the buy-order, funding, and tracking pickup, independent comparative inspection, and final delivery of each stone. The database of stones includes, for each stone, stone-weight, stone characteristics, price, and a grading lab certificate. The certificate uniquely identifies each stone and is electronically accessible by sellers, buyers, couriers, and authentication services. A buy command is communicated to seller and buyer. The transfer funds is electronically noted and communicated. The pickup by courier, interim delivery, inspection comparing the stone to the certificate, and subsequent delivery to buyer and release of funds is communicated to traders by emails, text messages, automated voice messages or IVR. Buyer and seller profiles establish communications channels and organizational managers are also permitted access and given communications. If time or place parameters are exceeded, increasing levels of alarm electronic communications are implemented. | 03-12-2009 |
20090125435 | Trading Plaftorm System and Method for Diamond and Precious Stone Transactions - The transaction method and system facilitates sales of diamonds or stones. A searchable database of stones includes, for each stone, an offer to sell, a weight-carat, other stone characteristics and an electronic copy of a grading lab certificate which uniquely identifies each stone from all other stones in the database. A search displays, for each stone, the offer and stone weight, stone characteristics and electronic access to the stone's certificate. The system permits a prospective buyer to “buy now,” which closes the transaction at the posted offer, or “bid now” wherein the system logs a bid value and an expiry time. Other bids are posted and displayed, in a primacy order until (a) the seller “buy now at the bid” or (b) withdraws the offer or (c) replaces the offer with a subsequent offer. Preferably, offers: displayed in time sequence and bids: displayed by primacy of price and expiry. | 05-14-2009 |
Patent application number | Description | Published |
20110138487 | Storage Device and Method for Using a Virtual File in a Public Memory Area to Access a Plurality of Protected Files in a Private Memory Area - A storage device and method for using a virtual file in a public memory area to access a plurality of protected files in a private memory area are disclosed. In one embodiment, a storage device receives a request from a host for access to a virtual file in the public memory area, wherein the virtual file is associated with a plurality of protected files stored in the private memory area. The storage device responds to the request by selecting and providing the host with access to one of the plurality of protected files stored in the private memory area. The storage device receives an additional request from the host for access to the virtual file and responds to the additional request by selecting and providing the host with access to a different one of the plurality of protected files stored in the private memory area. | 06-09-2011 |
20120042376 | Host Device and Method for Securely Booting the Host Device with Operating System Code Loaded From a Storage Device - A host device and method for securely booting the host device with operating system code loaded from a storage device are provided. In one embodiment, a host device is in communication with a storage device having a private memory area storing boot loader code and a public memory area storing operating system code. The host device instructs the storage device to initiate a boot mode and receives the boot loader code from the storage device. The host device executes the boot loader code which performs a security check and executes the operating system code loaded from the storage device only if the security check is successful. | 02-16-2012 |
20120260022 | HANDLING COMMANDS WITHIN A WRITE-ONCE READ-MANY STORAGE DEVICE CONFIGURATION - A storage device with a memory, a controller, and a host interface, and a method of handling commands in a storage device are provided to execute commands in a storage device having a write-once read-many device configuration, transparently to a host device. The memory containing a database having entries each entry for a logical memory address and containing information for converting that logical memory address to a redirected logical memory address that represents a memory location where data associated with that logical memory address actually resides. The controller performs, when the host interface is operatively coupled to a host device, to receive a command specifying a logical memory address and interpret the command based on information extracted from the database. The controller executes the command according to the information, transparently to the host device. | 10-11-2012 |