Patent application number | Description | Published |
20130107612 | Spin-Torque Transfer Magnetic Random Access Memory (STTMRAM) Device with Shared Transistor and Minimal Written Data Disturbance | 05-02-2013 |
20130272062 | Method and Apparatus for Programming a Spin-Transfer Torque Magnetic Random Access Memory (STTMRAM) Array - A spin-transfer torque memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ. | 10-17-2013 |
20130288396 | Embedded Magnetic Random Access Memory (MRAM) - A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed there through and are formed on top of the access transistor. A magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ. | 10-31-2013 |
20130302914 | Embedded Magnetic Random Access Memory (MRAM) - A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed there through and are formed on top of the access transistor. A magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ. | 11-14-2013 |
20140027830 | ACCESS TRANSISTOR WITH A BURIED GATE - A magnetic memory cell is formed including a magneto tunnel junction (MTJ) and an access transistor, which is used to access the MTJ in operation. The access transistor, which is formed on a silicon substrate, includes a gate, drain and source with the gate position substantially perpendicular to the plane of the silicon substrate thereby burying the gate and allowing more surface area on the silicon substrate for formation of additional memory cells. | 01-30-2014 |
20140192590 | MULTI-PORT MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read. | 07-10-2014 |
20140219013 | METHOD AND APPARATUS FOR READING A MAGNETIC TUNNEL JUNCTION USING A SEQUENCE OF SHORT PULSES - A magnetic random access memory (MRAM) array having a magnetic tunnel junction (MTJ) to be read using a magnetic state of the MTJ, the MTJ being read by applying a current there through. Further, the MRAM array has a reference MTJ, a sense amplifier coupled to the MTJ and the reference MTJ, the sense amplifier operable to compare the voltage of the MTJ to the reference MTJ in determining the state of the MTJ; a first capacitor coupled to the sense amplifier at a first end and to ground at a second end; and a second capacitor coupled to the sense amplifier at a first end and to ground at a second end, the first capacitor storing the, wherein short voltage pulses are applied to the first end of each of the first and second capacitors when reading the MTJ thereby makes the current flowing through the MTJ there through for small time intervals thereby avoiding read disturbance to the MTJ. | 08-07-2014 |
20140269040 | PULSE PROGRAMMING TECHNIQUES FOR VOLTAGE-CONTROLLED MAGNETORESISTIVE TUNNEL JUNCTION (MTJ) - A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ is programmed to the desired state. | 09-18-2014 |
20140269041 | EMULATION OF STATIC RANDOM ACCESS MEMORY (SRAM) BY MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks. | 09-18-2014 |
20150014800 | MTJ MEMORY CELL WITH PROTECTION SLEEVE AND METHOD FOR MAKING SAME - Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment of the present invention as applied to a memory cell comprises a top electrode layer, an upper magnetic layer, a barrier layer, a lower magnetic layer and a bottom electrode layer in a pillar formed on a landing pad; and a sleeve of dielectric material generally surrounding sidewalls of at least the barrier layer and the lower magnetic layer and partially surrounding the bottom electrode layer. The bottom electrode layer includes a ledge that extends under the sleeve of dielectric material and separates the sleeve of dielectric material from the landing pad under the bottom electrode layer. | 01-15-2015 |
20150014801 | Redeposition Control in MRAM Fabrication Process - Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode. | 01-15-2015 |
20150019804 | MAPPING OF RANDOM DEFECTS IN A MEMORY DEVICE - A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location. | 01-15-2015 |
20150043272 | Spin-Transfer Torque Magnetic Random Access Memory (STTMRAM) With Enhanced Write Current - A spin-transfer torque magnetic random access memory (STTMRAM) cell is disclosed. The memory cell comprises a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ. | 02-12-2015 |
20150078072 | METHOD AND APPARATUS FOR INCREASING THE RELIABILITY OF AN ACCESS TRANSITOR COUPLED TO A MAGNETIC TUNNEL JUNCTION (MTJ) - A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a parallel magnetic orientation, a bit line that is coupled to one end of the MTJ is raised to Vcc and a voltage that is the sum of Vcc and Vx is applied to the gate of the access transistor, with Vx being approximately the voltage at an opposite end of the MTJ. Further, the voltage of a Source Line (SL), which is coupled to the MTJ using a first transistor of a write driver that is also coupled to the SL, is regulated such that SL remains sufficiently above 0 volts to avoid violation of Vgs exceeding Vcc where Vgs is the gate to source voltage of the access transistor. | 03-19-2015 |
20150131369 | PULSE PROGRAMMING TECHNIQUES FOR VOLTAGE-CONTROLLED MAGNETORESISTIVE TUNNEL JUNCTION (MTJ) - A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ is programmed to the desired state. | 05-14-2015 |
20150146482 | METHOD AND APPARATUS FOR READING A MAGNETIC TUNNEL JUNCTION USING A SEQUENCE OF SHORT PULSES - A magnetic random access memory (MRAM) array having a magnetic tunnel junction (MTJ) to be read using a magnetic state of the MTJ, the MTJ being read by applying a current there through. Further, the MRAM array has a reference MTJ, a sense amplifier coupled to the MTJ and the reference MTJ, the sense amplifier operable to compare the voltage of the MTJ to the reference MTJ in determining the state of the MTJ; a first capacitor coupled to the sense amplifier at a first end and to ground at a second end; and a second capacitor coupled to the sense amplifier at a first end and to ground at a second end, the first capacitor storing the, wherein short voltage pulses are applied to the first end of each of the first and second capacitors when reading the MTJ thereby makes the current flowing through the MTJ there through for small time intervals thereby avoiding read disturbance to the MTJ. | 05-28-2015 |
Patent application number | Description | Published |
20110136443 | Transceivers - An RF transceiver apparatus comprises transmitter circuitry arranged to convert signals from a baseband frequency to RF transmission frequencies and receiver circuitry arranged to convert signals from RF reception frequencies to the baseband frequency. The transmitter and receiver circuitry each comprise three mixers arranged to convert a signals between the baseband frequency, a first intermediate frequency; a second intermediate frequency that is higher than the transmission frequencies; and a second intermediate frequency to the transmission frequency. | 06-09-2011 |
20130195151 | FIELD PROGRAMMABLE TRANSCEIVER CIRCUITS - A transceiver circuit comprising a transmit path and a receive path, the transmit path comprising at least one digital to analogue converter for converting a digital input signal to an analogue signal, at least one filter for filtering the analogue signal, at least one first frequency synthesizer for producing a first synthesized RF signal, at least one mixer for mixing the analogue signal with the RF signal to produce an RF output, and at least one amplifier for amplifying the RF output for transmission; and the receive path comprising at least one second amplifier for amplifying a received RF input, at least one second frequency synthesizer for generating a second synthesized RF signal, at least one second mixer for mixing the amplified RF input with the second synthesized RF signal to produce a baseband signal, at least one second filter for filtering the baseband signal, and at least one analogue to digital converter for converting the baseband signal to a digital output signal, at least one switch arranged to selectively connect together different points of the circuit thereby to bypass at least one component of the circuit and a control input connected to the at least one switch and arranged to receive control signals for controlling operation of the at least one switch. | 08-01-2013 |
20140235182 | TRANSMITTER AND RECEIVER CIRCUITS - An RF transceiver apparatus has transmitter circuitry receiving transmission signals at a transmitter baseband frequency and converting the signals to a transmission frequency, and receiver circuitry receiving signals at a reception frequency and converting to a receiver baseband frequency. A first digital local oscillator and a first mixer convert between the transmitter baseband frequency and a transmitter intermediate frequency. A second digital local oscillator and a second mixer convert between a receiver intermediate frequency and the receiver baseband frequency. A third mixer frequency receives a local oscillator signal for frequency conversion between the transmitter intermediate frequency and the transmission frequency. A fourth mixer frequency receives a local oscillator signal for frequency conversion between the reception frequency and the receiver intermediate frequency. A third local oscillator produces an RF oscillator signal to the third mixer and the fourth mixer to provide the local oscillator signal. | 08-21-2014 |
Patent application number | Description | Published |
20140359560 | DEFINING ATTRIBUTES OF VARIABLES IN A STATE CHART OF A TECHNICAL COMPUTING ENVIRONMENT - A device may receive a model generated via a technical computing environment, where the model included a state chart with one or more variables. The device may receive a selection of a particular variable from the state chart, and may provide, for display and based on the selection, a user interface for defining attributes associated with the particular variable. The device may receive, via the user interface, one or more user-defined attributes for the particular variable, where at least one of the one or more user-defined attributes is defined independently of a reference to the particular variable. The device may apply the one or more user-defined attributes in the model and the state chart. | 12-04-2014 |
20140359561 | IMPLICIT EVENT BROADCAST IN A STATE CHART OF A TECHNICAL COMPUTING ENVIRONMENT - A device may receive a state chart generated via a technical computing environment. The state chart may include a first state block and a second state block, and the second state block may include textual code understood by a textual engine of the technical computing environment. The device may receive, in association with the second state block, an implicit event command that references an event associated with the first state block, and may initiate execution of the state chart. The device may receive, during execution of the state chart, an indication of occurrence of the event associated with the first state block, and may initiate the second state block based on the indication. | 12-04-2014 |
20140359566 | RESOLUTION OF TEXTUAL CODE IN A GRAPHICAL HIERARCHICAL MODEL OF A TECHNICAL COMPUTING ENVIRONMENT - A device may receive a chart generated via a technical computing environment, where the chart includes a textual portion and a graphical portion, and the graphical portion includes state information. The device may parse the chart into the textual portion and the graphical portion, and may process the textual portion with a textual engine of the technical computing environment to generate textual results. The device may process the graphical portion with a graphical engine of the technical computing environment to generate graphical results, and may combine the textual results with the graphical results to generate chart results. The device may output or store the chart results. | 12-04-2014 |
20140359567 | TEXTUAL CODE PROVIDED IN TEMPORAL AND CHANGE OPERATORS OF A TECHNICAL COMPUTING ENVIRONMENT - A device may receive a state chart generated via a technical computing environment, where the state chart may include at least one state block. The device may receive a time-based or an event-based operator associated with the at least one state block. The time-based or the event-based operator may include textual code understood by a textual engine of the technical computing environment. The device may initiate execution of the state chart, and may process, during the execution the state chart, the time-based or the event-based operator and the at least one state block with a graphical engine of the technical computing environment to generate graphical results. The device may process, during the execution of the state chart, the textual code of the time-based or the event-based operator with the textual engine to generate textual results, and may combine the graphical results with the textual results to generate chart results. | 12-04-2014 |
20140359568 | TIME-BASED OPERATIONS VIA TEXTUAL CODE IN A TECHNICAL COMPUTING ENVIRONMENT - A device may receive a state chart generated via a technical computing environment. The state chart may include a state block with a single section of textual code. The single section of textual code may include a time-based portion and an output portion. The device may initiate execution of the state chart, and may process, during the execution of the state chart, the time-based portion with a graphical engine of the technical computing environment to generate a time-based method. The device may process, during the execution of the state chart, the output portion with a textual engine of the technical computing environment to generate an output method. The device may provide the time-based method and the output method in output code, where the time-based method may be separate from the output method in the output code. | 12-04-2014 |
20140359569 | GRAPHICAL FUNCTION SPECIALIZATION - A device receives a state chart generated via a technical computing environment. The state chart includes a function block that includes a function that includes function input(s)/output(s). The state chart includes a state block that includes a function call to the function of the function block. The function call includes call input(s)/output(s). The device initiates execution of the state chart, parses the function into the function input(s)/output(s), and parses the function call into the call input(s)/output(s). The device processes, during the execution of the state chart, the function input(s)/output(s) with a graphical engine of the technical computing environment to generate function-related code. The device processes, during the execution of the state chart, the call input(s)/output(s) with a textual engine of the technical computing environment to generate function call-related code, and provides the function-related code and the function call-related code in generated code. | 12-04-2014 |