Patent application number | Description | Published |
20080203590 | INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE WITH OVERLAY KEY AND ALIGNMENT KEY AND METHOD OF FABRICATING THE SAME - An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench. | 08-28-2008 |
20080206686 | METHOD OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming fine patterns on a semiconductor substrate includes forming a first pattern, including first line patterns having a feature size F and an arbitrary pitch P, and forming a second pattern, including second line patterns disposed between adjacent first line patterns, to form a fine pattern having a half pitch P/2, the first and second line patterns being repeated in the first direction. A gap is formed in at least one first line pattern in a second direction, perpendicular to the first direction, to connect second line patterns positioned on each side of the first line pattern through the gap. At least one jog pattern, extending in the first direction, is formed from at least one first line pattern adjacent to the connected second line patterns. The jog pattern causes a gap in at least one of the connected second line patterns in the second direction. | 08-28-2008 |
20080220611 | Method of forming fine patterns of semiconductor devices using double patterning - A method of forming fine patterns of semiconductor device according to an example embodiment may include forming a plurality of multi-layered mask patterns by stacking first mask patterns and buffer mask patterns on an etch film to be etched on a substrate, forming, on the etch film, second mask patterns in spaces between the plurality of multi-layered mask patterns, removing the second mask patterns to expose upper surfaces of the first mask patterns, and forming the fine patterns by etching the etch film using the first and second mask patterns as an etch mask. This example embodiment may result in the formation of diverse dimensions at diverse pitches on a single substrate. | 09-11-2008 |
20080280381 | Method of forming a fine pattern of a semiconductor device using a resist reflow measurement key - In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key. | 11-13-2008 |
20090034336 | Flash memory device having improved bit-line layout and layout method for the flash memory device - Provided are a flash memory device having an improved bit-line layout and a layout method for the flash memory device. The flash memory device in which bit lines are disposed based on double patterning technology (DPT), may include at least one main bit line connected to a cell string including a memory cell storing data, at least one dummy bit line disposed parallel to the at least one main bit line, and a common source line transferring a common source voltage, and disposed on a different layer from a layer on which the at least one main bit line and the at least one dummy bit line are disposed, wherein the at least one dummy bit line may include a first dummy bit line transferring a first voltage and a second dummy bit line transferring a second voltage. | 02-05-2009 |
20090283145 | Semiconductor Solar Cells Having Front Surface Electrodes - Solar cells include a substrate having a light collecting surface thereon and a P-N rectifying junction within the substrate. The P-N rectifying junction includes a base region of first conductivity type (e.g., p-type) and a semiconductor layer of second conductivity type extending between the base region and the light collecting surface. A trench is also provided, which extends through the semiconductor layer and into the base region. First and second electrodes are provided adjacent the light collecting surface. The first electrode is electrically coupled to the semiconductor layer and the second electrode is electrically coupled to the base region, at a location adjacent a bottom of the trench. | 11-19-2009 |
20090286347 | Methods of Forming Semiconductor Solar Cells Having Front Surface Electrodes - Solar cells include a substrate having a light collecting surface thereon and a P-N rectifying junction within the substrate. The P-N rectifying junction includes a base region of first conductivity type (e.g., p-type) and a semiconductor layer of second conductivity type extending between the base region and the light collecting surface. A trench is also provided, which extends through the semiconductor layer and into the base region. First and second electrodes are provided adjacent the light collecting surface. The first electrode is electrically coupled to the semiconductor layer and the second electrode is electrically coupled to the base region, at a location adjacent a bottom of the trench. | 11-19-2009 |
20090288702 | Solar Cell and Solar Cell Module Using the Same - Provided is a solar cell module having improved energy efficiency. The solar cell module includes a frame, first solar cells arranged at the frame, and second solar cells smaller than the first solar cells. The second solar cells are disposed in regions surrounded by the first solar cells. The first solar cells have a substantially circular shape. The second solar cells have a rectangular shape, and each of the second solar cells is surrounded by four of the first solar cells. | 11-26-2009 |
20100124114 | Semiconductor Device and Layout Method for the Semiconductor Device - Provided is a semiconductor device comprising: a plurality of bit line patterns; a plurality of pad patterns that are respectively connected to the plurality of bit line patterns; and at least one contact that is formed on each of the plurality of pad patterns, wherein the pitch of the plurality of pad patterns is greater than the pitch of the plurality of bit line patterns. The bit line patterns may be formed using a double patterning technology (DPT). | 05-20-2010 |
20110048529 | SOLAR CELL - A solar cell includes a semiconductor substrate having a plurality of contact holes penetrating therethrough, from one surface to the opposing surface and including a part having a first conductive layer selected from p-type and n-type and a part having a second conductive layer different from the first conductive layer and selected from p-type and n-type semiconductor, a first electrode formed on one surface of the semiconductor substrate and electrically connected with the part having the first conductive layer, a second electrode formed on the other surface of the semiconductor substrate and electrically connected with the first electrode, and a third electrode formed on the same surface as in the second electrode and electrically connected with the part having the second conductive layer of the semiconductor substrate, wherein the plurality of contact holes form a contact hole group, and the first electrode and the second electrode are connected through one or more of the plurality of contact holes of the contact hole group. | 03-03-2011 |
20110126906 | SOLAR CELL AND METHOD OF MANUFACTURING THE SAME - A solar cell includes a semiconductor substrate, an n+ region and a p+ region disposed on the semiconductor substrate, a first electrode electrically connected to the n+ region, and a second electrode electrically connected to the p+ region. A trench formed in the semiconductor substrate separates the n+ region from the p+ region. | 06-02-2011 |
20110126907 | SOLAR CELL AND METHOD OF MANUFACTURING THE SAME - A solar cell includes; a semiconductor substrate, an n+ region disposed on a surface of the semiconductor substrate, a plurality of first electrodes connected to the n+ region, a p+ region disposed on the surface of the semiconductor substrate and separated from the n+ region, a second electrode connected to the p+ region, and a first dielectric layer which has a positive fixed charge and is disposed between adjacent first electrodes of the plurality of first electrodes, and a method of manufacturing the same. | 06-02-2011 |
20110284060 | SOLAR CELL AND METHOD OF FABRICATING THE SAME - A solar cell and method of fabricating the same using a simplified process. The solar cell includes a semiconductor substrate of a first conductivity type having a front surface configured to receive sunlight and a back surface opposite to the front surface, and a diffusion region of the first conductivity type and a diffusion region of a second conductivity type extending from the back surface of the semiconductor substrate into the semiconductor substrate to a predetermined depth, wherein the diffusion region of the first conductivity type is counter doped with both a dopant of the first conductivity type and a dopant of the second conductivity type. | 11-24-2011 |
20110306164 | METHOD FOR MANUFACTURING SOLAR CELL - A method for manufacturing a solar cell according to an exemplary embodiment includes: forming a first doping film on a substrate; patterning the first doping film so as to form a first doping film pattern and so as to expose a portion of the substrate; forming a diffusion prevention film on the first doping film pattern so as to cover the exposed portion of the substrate; etching the diffusion prevention film so as to form spacers on lateral surfaces of the first doping film pattern; forming a second doping film on the first doping film pattern so as to cover the spacer and exposed substrate; forming a first doping region on the substrate surface by diffusing an impurity from the first doping film pattern into the substrate; and forming a second doping region on the substrate surface by diffusing an impurity from the second doping film pattern into the substrate. | 12-15-2011 |
20120012176 | SOLAR CELL AND METHOD OF MANUFACTURING THE SAME - A solar cell includes a substrate, a doped pattern, a contact layer, and an electrode. The substrate includes a first surface onto which sunlight is incident and a second surface facing the first surface. The doped pattern is formed on the second surface of the substrate and the contact layer is formed on the doped pattern. The electrode is formed on the contact layer and is electrically connected to the doped pattern. Accordingly, a contact resistance between the substrate and the electrode may be decreased, so that the doped pattern and the electrode may be uniformly formed and a power efficiency of the solar cell may be improved. | 01-19-2012 |
20120270365 | METHOD FOR MANUFACTURING SOLAR CELL - A method for manufacturing a solar cell according to an exemplary embodiment includes: forming a first doping film on a substrate; patterning the first doping film so as to form a first doping film pattern and so as to expose a portion of the substrate; forming a diffusion prevention film on the first doping film pattern so as to cover the exposed portion of the substrate; etching the diffusion prevention film so as to form spacers on lateral surfaces of the first doping film pattern; forming a second doping film on the first doping film pattern so as to cover the spacer and exposed substrate; forming a first doping region on the substrate surface by diffusing an impurity from the first doping film pattern into the substrate; and forming a second doping region on the substrate surface by diffusing an impurity from the second doping film pattern into the substrate. | 10-25-2012 |