Patent application number | Description | Published |
20140091381 | SUPPORT LINES TO PREVENT LINE COLLAPSE IN ARRAYS - Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be provided to prevent the collapse of closely spaced device structures during fabrication. In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be set in place prior to performing a high aspect ratio word line etch for forming the NAND strings. The one or more mechanical support structures may comprise one or more fin supports that are arranged in a bit line direction. In another example, the one or more mechanical support structures may be developed during the word line etch for forming the NAND strings. | 04-03-2014 |
20140151778 | Select Gate Formation for Nanodot Flat Cell - Methods of fabricating a memory device include forming a tunnel oxide layer over a memory cell area of a semiconductor substrate, forming a floating gate layer over the tunnel oxide layer in the memory cell area, the floating gate layer comprising a plurality of nanodots embedded in a dielectric material, forming a blocking dielectric layer over the floating gate layer in the memory cell area, removing portions of the blocking dielectric layer, the floating gate layer, the tunnel oxide layer, and the semiconductor substrate in the memory cell area to form a first plurality of isolation trenches, and forming isolation material within the first plurality of isolation trenches. | 06-05-2014 |
20140175530 | THREE DIMENSIONAL NAND DEVICE WITH SILICIDE CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers. | 06-26-2014 |
20140239365 | METHOD FOR USING NANOPARTICLES TO MAKE UNIFORM DISCRETE FLOATING GATE LAYER - A memory cell including a control gate located over a floating gate region. The floating gate region includes discrete doped semiconducting or conducting regions separated by an insulator and the discrete doped semiconducting or conducting regions have a generally cylindrical shape or a quasi-cylindrical shape. | 08-28-2014 |
20140252447 | Nanodot-Enhanced Hybrid Floating Gate for Non-Volatile Memory Devices - A memory device and a method of making a memory device that includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a floating gate located over the tunnel dielectric layer, the floating gate comprising a continuous layer of an electrically conductive material and at least one protrusion of an electrically conductive material facing the tunnel dielectric layer and electrically shorted to the continuous layer, a blocking dielectric region located over the floating gate, and a control gate located over the blocking dielectric layer. | 09-11-2014 |
20140346583 | INVERTED-T WORD LINE AND FORMATION FOR NON-VOLATILE STORAGE - A non-volatile memory system, comprising non-volatile storage device with word lines having an inverted T-shape over floating gates. The inverted T-shape shape has a wider bottom portion and a thinner top portion. The thinner top portion increases the separation between adjacent word lines relative to the separation between the wider bottom portions. An air gap may separate adjacent word lines. The thinner top portion of the word lines increases the path length between adjacent word lines. The likelihood of word line to word line short may be decreased by reducing the electric field between adjacent word lines. | 11-27-2014 |
20140346584 | MEMORY DEVICE WITH CONTROL GATE OXYGEN DIFFUSION CONTROL AND METHOD OF MAKING THEREOF - An embodiment relates to a memory device that includes a semiconductor channel, a tunnel dielectric located over the semiconductor channel, a charge storage region located over the tunnel dielectric, a blocking dielectric located over the charge storage region, and a control gate located over the blocking dielectric. An interface between the blocking dielectric and the control gate substantially prevents oxygen diffusion from the blocking dielectric into the control gate. | 11-27-2014 |
20150072488 | THREE DIMENSIONAL NAND DEVICE WITH SILICIDE CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers. | 03-12-2015 |