Patent application number | Description | Published |
20130256818 | METHODS OF FORMING SPIN TORQUE DEVICES AND STRUCTURES FORMED THEREBY - Methods of forming spin torque microelectronic devices are described. Those methods may include forming a free FM layer on a substrate, forming a non-magnetic layer on the free FM layer, forming at least three input pillars on the non-magnetic layer, and forming an output pillar on the non-magnetic layer to form a majority gate device. | 10-03-2013 |
20140092664 | Associative Memory Oscillator Array - An embodiment of the invention includes an analog associative memory, which includes an array of coupled voltage or current controlled oscillators, that matches patterns based on shifting frequencies away from a center frequency of the oscillators. The test and memorized patterns are programmed into the oscillators by varying the voltage or current that controls the oscillators. Matching patterns result in smaller shifts of frequencies and enable synchronization of oscillators. Non-matching patterns result in larger shifts and preclude synchronization of oscillators. In one embodiment the patterns each include binary data and the pattern matching is based on discrete shifts. In one embodiment the patterns each include grayscale data and the pattern matching is based on continuously-varied shifts. Other embodiments are described herein. | 04-03-2014 |
20140139265 | HIGH SPEED PRECESSIONALLY SWITCHED MAGNETIC LOGIC - High speed precessionally switched magnetic logic devices and architectures are described. In a first example, a magnetic logic device includes an input electrode having a first nanomagnet and an output electrode having a second nanomagnet. The spins of the second nanomagnet are non-collinear with the spins of the first nanomagnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. In a second example, a magnetic logic device includes an input electrode having an in-plane nanomagnet and an output electrode having a perpendicular magnetic anisotropy (PMA) magnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. | 05-22-2014 |
20140142915 | METHODS AND APPARATUS FOR MODELING AND SIMULATING SPINTRONIC INTEGRATED CIRCUITS - Described are apparatus and method for simulating spintronic integrated circuit (SPINIC), the method comprising: generating a spin netlist indicating connections of spin nodes of spin circuits and nodes of general circuits; and modifying a modified nodal analysis (MNA) matrix for general circuits to generate a spin MNA matrix for solving spin circuits and general circuits of the spin netlist. | 05-22-2014 |
20140146133 | TRANSPARENT HOLOGRAPHIC DISPLAY WITH DYNAMIC IMAGE CONTROL - Generally, this disclosure provides systems and methods for generating three dimensional holographic images on a transparent display screen with dynamic image control. The system may include a transparent display screen that includes an array of pixels; a driver circuit configured to control each of the pixels in the array of pixels such that the transparent display screen displays an interference fringe pattern, the interference fringe pattern associated with a hologram; and a coherent light source configured to illuminate the transparent display screen with coherent light, wherein transformation of the coherent light by the interference fringe pattern generates a three dimensional holographic image. | 05-29-2014 |
20140152383 | INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR PRODUCING THE SAME - Three dimensional integrated circuits including semiconductive organic materials are described. In some embodiments, the three dimensional integrated circuits include one or more electronic components that include a semiconductive region formed of one or more semiconductive organic materials. The electronic components of the three dimensional integrated circuits may also include insulating regions formed from organic insulating materials, and conductive regions form from conductive materials. The three dimensional integrated circuits may be formed by an additive manufacturing process such as three dimensional printing. Apparatus and methods for producing and testing three dimensional integrated circuits are also described. | 06-05-2014 |
20140169801 | SEMICONDUCTOR PACKAGE WITH OPTICAL PORT - Described herein are technologies related to a semiconductor package that is installed in a portable device for data communications. More particularly, the semiconductor package that contains a memory, a digital logic chip, and an optical port in a single module or mold is described. | 06-19-2014 |
20140219012 | MAGNETIC STATE ELEMENT AND CIRCUITS - Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic demultiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices. | 08-07-2014 |
20140269034 | INTEGRATED CAPACITOR BASED POWER DISTRIBUTION - An embodiment provides power (having low voltage, high current, and high current density) to ultra low voltage non-CMOS based devices using a distributed capacitor that is integrated onto the same chip as the non-CMOS devices. For example, an embodiment provides a spin logic gate adjacent dielectric material and first and second plates of a capacitor. The capacitor discharges low voltage/high current to the spin logic gate using a step down switched mode power supply that charges numerous capacitors during one clock cycle (using a switching element configured in a first orientation) and discharges power from the capacitors during the opposite clock cycle (using the switching element configured in a second orientation). The capacitors discharge the current out of plane and to the spin logic devices without having to traverse long power dissipating interconnect paths. Other embodiments are described herein. | 09-18-2014 |
20140269035 | CROSS POINT ARRAY MRAM HAVING SPIN HALL MTJ DEVICES - Cross point array magnetoresistive random access memory (MRAM) implementing spin hall magnetic tunnel junction (MTJ)-based devices and methods of operation of such arrays are described. For example, a bit cell for a non-volatile memory includes a magnetic tunnel junction (MTJ) stack disposed above a substrate and having a free magnetic layer disposed above a dielectric layer disposed above a fixed magnetic layer. The bit cell also includes a spin hall metal electrode disposed above the free magnetic layer of the MTJ stack. | 09-18-2014 |