Dhong
Hun-Jong Dhong, Seoul KR
Patent application number | Description | Published |
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20090197845 | Method for treating olfactory disorder - Disclosed is a method for treating olfactory disorders, which comprises administering to a patient a therapeutically effective amount of 3-β-hydroxymethylglutarate CoA (HMG-CoA) reductase, which has excellent effects of protecting and regenerating olfactory nerve. | 08-06-2009 |
Sang Hoo Dhong, Austin, TX US
Patent application number | Description | Published |
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20080263336 | Processor Having Efficient Function Estimate Instructions - High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic. | 10-23-2008 |
20090024684 | Method for Controlling Rounding Modes in Single Instruction Multiple Data (SIMD) Floating-Point Units - A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively. | 01-22-2009 |
20090077155 | HIGH SPEED ADDER DESIGN FOR A MULTIPLY-ADD BASED FLOATING POINT UNIT - A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays. | 03-19-2009 |
Sang Hoo Dhong, Hsinchu City TW
Patent application number | Description | Published |
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20140212815 | Charged Particle Lithography System With a Long Shape Illumination Beam - A system includes an integrated circuit (IC) design data base having a feature, a source configured to generate a radiation beam, a pattern generator (PG) including a mirror array plate and an electrode plate disposed over the mirror array plate, wherein the electrode plate includes a lens let having a first dimension and a second dimension perpendicular to the first dimension with the first dimension larger than the second dimension so that the lens let modifies the radiation beam to form the long shaped radiation beam, and a stage configured secured the substrate. The system further includes an electric field generator connecting the minor array plate. The mirror array plate includes a mirror. The mirror absorbs or reflects the radiation beam. The radiation beam includes electron beam or ion beam. The second dimension is equal to a minimum dimension of the feature. | 07-31-2014 |
Sang Hoo Dhong, Hsin-Chu City TW
Patent application number | Description | Published |
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20140268078 | ELECTRON BEAM LITHOGRAPHY SYSTEMS AND METHODS INCLUDING TIME DIVISION MULTIPLEX LOADING - The present disclosure provides a systems and methods for e-beam lithography. One system includes an electron source operable to produce a beam and an array of pixels operable to pattern the beam. Control circuitry is spaced a distance from and coupled to the array of pixels. The control circuitry uses time domain multiplex loading (TMDL) to control the array of pixels. | 09-18-2014 |
20150069501 | SEMICONDUCTOR ARRANGEMENT - A semiconductor arrangement includes a first semiconductor device including a first type region having a first conductivity type and a second type region having a second conductivity type. The semiconductor arrangement includes a second semiconductor device adjacent the first semiconductor device. The second semiconductor device includes a third type region having a third conductivity type and a fourth type region having a fourth conductivity type. The semiconductor arrangement includes a first insulator layer including a first insulator portion around at least some of the first semiconductor device and a second insulator portion around at least some of the second semiconductor device. The first insulator portion has a first insulator height, and the second insulator portion has a second insulator height. The first insulator height is different than the second insulator height. A method of forming a semiconductor arrangement is provided. | 03-12-2015 |