Patent application number | Description | Published |
20100142850 | System, method, and product for scanning of biological materials - An embodiment of a scanning system is described including optical elements that direct an excitation beam at a probe array, detectors that receive reflected intensity data responsive to the excitation beam, where the reflected intensity data is responsive to a focusing distance between an optical element and the probe array, a transport frame that adjusts the focusing distance in a direction with respect to the probe array, an auto-focuser that determines a best plane of focus based upon characteristics of the reflected intensity data of at least two focusing distances where the detectors further receive pixel intensity values based upon detected emissions from a plurality of probe features disposed on the probe array at the best plane of focus, and an image generator that associates each of the pixel intensity values with at least one image pixel position of a probe array based upon one or more position correction values. | 06-10-2010 |
20110207621 | Assays Based on Liquid Flow over Arrays - Flow-through assay reaction chamber ( | 08-25-2011 |
20110243411 | System, method, and product for scanning of biological materials - An embodiment of a scanning system is described including optical elements that direct an excitation beam at a probe array, detectors that receive reflected intensity data responsive to the excitation beam, where the reflected intensity data is responsive to a focusing distance between an optical element and the probe array, a transport frame that adjusts the focusing distance in a direction with respect to the probe array, an auto-focuser that determines a best plane of focus based upon characteristics of the reflected intensity data of at least two focusing distances where the detectors further receive pixel intensity values based upon detected emissions from a plurality of probe features disposed on the probe array at the best plane of focus, and an image generator that associates each of the pixel intensity values with at least one image pixel position of a probe array based upon one or more position correction values. | 10-06-2011 |
20110319279 | Assays Based on Liquid Flow Over Arrays | 12-29-2011 |
20120235016 | System, Method, and Product for Scanning of Biological Materials - An embodiment of a scanning system is described including optical elements that direct an excitation beam at a probe array, detectors that receive reflected intensity data responsive to the excitation beam, where the reflected intensity data is responsive to a focusing distance between an optical element and the probe array, a transport frame that adjusts the focusing distance in a direction with respect to the probe array, an auto-focuser that determines a best plane of focus based upon characteristics of the reflected intensity data of at least two focusing distances where the detectors further receive pixel intensity values based upon detected emissions from a plurality of probe features disposed on the probe array at the best plane of focus, and an image generator that associates each of the pixel intensity values with at least one image pixel position of a probe array based upon one or more position correction values. | 09-20-2012 |
Patent application number | Description | Published |
20080265380 | METHOD FOR FABRICATING A HIGH-K DIELECTRIC LAYER - One inventive aspect relates to a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus about 10%. The method further comprises thinning the high-k dielectric layer to a second thickness. Another inventive aspect relates to a semiconductor device comprising a high-k dielectric layer as fabricated by the method. | 10-30-2008 |
20090196091 | Self-aligned phase change memory - A self-aligned phase change memory may be formed by blanket depositing a number of layers and then using patterning techniques to define the individual cells. In one embodiment, a layer of phase change material may be blanket deposited over a lower electrode material. The structure may then be patterned and etched to form a plurality of spaced, parallel elongate first strips. Those strips may then be covered with a filler material, planarized, and then patterned again in a transverse direction to form a plurality of transverse, spaced, parallel second strips. The resulting structure then has singulated phase change material with connections in at least one of the row or column direction. The singulated the phase change material is self-aligned to underlying and overlying electrodes. | 08-06-2009 |
20120025164 | VARIABLE RESISTANCE MEMORY WITH A SELECT DEVICE - According to various embodiments, a variable resistance memory element and memory element array that uses variable resistance changes includes a select device, such as an ovonic threshold switch. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element. | 02-02-2012 |
20120262835 | METHOD FOR FABRICATING A DRAM CAPACITOR - A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO | 10-18-2012 |
20120287553 | METHOD FOR FABRICATING A DRAM CAPACITOR HAVING INCREASED THERMAL AND CHEMICAL STABILITY - A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode film. The first electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the first electrode film. A high-k dielectric film is formed over the first electrode film. A second electrode film is formed over the dielectric film. The second electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the second electrode film. The dopants and their distribution are chosen so that the crystal structure of the surface of the electrode is not degraded if the electrode is to be used as a templating structure for subsequent layer formation. Additionally, the dopants and their distribution are chosen so that the work function of the electrodes is not degraded. | 11-15-2012 |
20120322220 | METHOD OF PROCESSING MIM CAPACITORS TO REDUCE LEAKAGE CURRENT - A method for processing dielectric materials and electrodes to decrease leakage current is disclosed. The method includes a post dielectric anneal treatment in an oxidizing atmosphere to reduce the concentration of oxygen vacancies in the dielectric material. The method further includes a post metallization anneal treatment in an oxidizing atmosphere to reduce the concentration of interface states at the electrode/dielectric interface and to further reduce the concentration of oxygen vacancies in the dielectric material. | 12-20-2012 |
20120322221 | MOLYBDENUM OXIDE TOP ELECTRODE FOR DRAM CAPACITORS - A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO | 12-20-2012 |
20120329235 | WET ETCH AND CLEAN CHEMISTRIES FOR MoOx - A method of removing non-noble metal oxides from material (e.g., semiconductor material) used to make a microelectronic device includes providing the material comprising traces of the conducting non-noble metal oxides; applying a chemical mixture (or chemical solution) to the material; removing the traces of the non-noble metal oxides from the material; and removing the chemical mixture from the material. The non-noble metal oxides comprise MoO | 12-27-2012 |
20130052790 | DOPING APPROACH OF TITANIUM DIOXIDE FOR DRAM CAPACITORS - A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a doped material formed from a first dopant in concert with a second dopant wherein the second dopant has a different physical size from the first dopant and the presence of the second dopant influences the solubility of the first dopant in the dielectric material. The dielectric material maintains a high k-value while minimizing the leakage current and the EOT value | 02-28-2013 |
20130052792 | HIGH PERFORMANCE DIELECTRIC STACK FOR DRAM CAPACITOR - A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value. | 02-28-2013 |
20130071986 | PARTIAL ETCH OF DRAM ELECTRODE - A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is first etched and then annealed in a reducing atmosphere or an inert atmosphere to promote the formation of a desired crystal structure and to remove oxygen rich compounds. The binary metal compound may be a metal oxide. Etching the metal oxide (i.e. molybdenum oxide) may result in the removal of oxygen rich phases and the formation of a first electrode material (i.e. MoO | 03-21-2013 |
20130071987 | Band Gap Improvement In DRAM Capacitors - A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic % and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO | 03-21-2013 |
20130071988 | INTERFACIAL LAYER FOR DRAM CAPACITOR - A method for reducing leakage current in DRAM capacitor stacks by introducing dielectric interface layers between the electrodes and the bulk dielectric material. The dielectric interface layers are typically amorphous dielectric materials with a k value between about 10 and about 30 and are less than about 1.5 nm in thickness. Advantageously, the thickness of each of the dielectric interface layers is less than 1.0 nm. In some cases, only a single dielectric interface layer is used between the bulk dielectric material and the second electrode. | 03-21-2013 |
20130071989 | SINGLE-SIDED NON-NOBLE METAL ELECTRODE HYBRID MIM STACK FOR DRAM DEVICES - A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited first dielectric layer. The first high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous, doped high k second dielectric material is form on the first dielectric layer. The dopant concentration and the thickness of the second dielectric layer are chosen such that the second dielectric layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the second dielectric layer is formed on the second dielectric layer. | 03-21-2013 |
20130115750 | BLOCKING LAYERS FOR LEAKAGE CURRENT REDUCTION IN DRAM DEVICES - A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer. | 05-09-2013 |
20130119513 | Adsorption Site Blocking Method for Co-Doping ALD Films - A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material. | 05-16-2013 |
20130122678 | ADSORPTION SITE BLOCKING METHOD FOR CO-DOPING ALD FILMS - A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material. | 05-16-2013 |
20130122681 | TOP ELECTRODE TEMPLATING FOR DRAM CAPACITOR - A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer. | 05-16-2013 |
20130122682 | ANNEAL TO MINIMIZE LEAKAGE CURRENT IN DRAM CAPACITOR - A method for forming a DRAM MIM capacitor stack comprises forming a first electrode layer, annealing the first electrode layer, forming a dielectric layer on the first electrode layer, annealing the dielectric layer, forming a second electrode layer on the dielectric layer, annealing the second electrode layer, patterning the capacitor stack, and annealing the capacitor stack for times greater than about 10 minutes, and advantageously greater than about 1 hour, at low temperatures (less than about 300 C) in an atmosphere containing less than about 25% oxygen and preferably less than about 10% oxygen. | 05-16-2013 |
20130127015 | Band Gap Improvement In DRAM Capacitors - A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO | 05-23-2013 |
20130140619 | High Performance Dielectric Stack for DRAM Capacitor - A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value. | 06-06-2013 |
20130143383 | METHOD OF FORMING AN ALD MATERIAL - In some embodiments of the present invention, methods are developed wherein a gas flow of an electron donating compound (EDC) is introduced in sequence with a precursor pulse and alters the deposition of the precursor material. In some embodiments, the EDC pulse is introduced sequentially with the precursor pulse with a purge step used to remove the non-adsorbed EDC from the process chamber before the precursor is introduced. In some embodiments, the EDC pulse is introduced using a vapor draw technique or a bubbler technique. In some embodiments, the EDC pulse is introduced in the same gas distribution manifold as the precursor pulse. In some embodiments, the EDC pulse is introduced in a separate gas distribution manifold from the precursor pulse. | 06-06-2013 |
20130143384 | HIGH PERFORMANCE DIELECTRIC STACK FOR DRAM CAPACITOR - A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value. | 06-06-2013 |
20130154057 | Method for Fabricating a DRAM Capacitor - A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO | 06-20-2013 |
20130330902 | ENHANCED NON-NOBLE ELECTRODE LAYERS FOR DRAM CAPACITOR CELL - A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 μΩ cm. Advantageously, the electrode materials are conductive molybdenum oxide. | 12-12-2013 |
20130330903 | MANUFACTURABLE HIGH-K DRAM MIM CAPACITOR STRUCTURE - A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin (3 nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material. | 12-12-2013 |
20140183697 | High Work Function, Manufacturable Top Electrode - Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer. | 07-03-2014 |
20140187016 | High Work Function, Manufacturable Top Electrode - Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer. | 07-03-2014 |
Patent application number | Description | Published |
20100163818 | FORMING A CARBON PASSIVATED OVONIC THRESHOLD SWITCH - By making an ovonic threshold switch using a carbon interfacial layer having a thickness of less than or equal to ten percent of the thickness of the associated electrode, cycle endurance may be improved. In some embodiments, a glue layer may be used between the carbon and the chalcogenide of the ovonic threshold switch. The glue layer may be effective to improve adherence between carbon and chalcogenide. | 07-01-2010 |
20130056851 | Molybdenum Oxide Top Electrode for DRAM Capacitors - A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO | 03-07-2013 |
20130113079 | Blocking Layers for Leakage Current Reduction in DRAM Devices - A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer. | 05-09-2013 |
20130119512 | Top Electrode Templating for DRAM Capacitor - A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer. | 05-16-2013 |
20130119515 | METHOD FOR FABRICATING A DRAM CAPACITOR HAVING INCREASED THERMAL AND CHEMICAL STABILITY - A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode film. The first electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the first electrode film. A high-k dielectric film is formed over the first electrode film. A second electrode film is formed over the dielectric film. The second electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the second electrode film. The dopants and their distribution are chosen so that the crystal structure of the surface of the electrode is not degraded if the electrode is to be used as a templating structure for subsequent layer formation. Additionally, the dopants and their distribution are chosen so that the work function of the electrodes is not degraded. | 05-16-2013 |
20130122683 | BLOCKING LAYERS FOR LEAKAGE CURRENT REDUCTION IN DRAM DEVICES - A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer. | 05-16-2013 |
20130196257 | Method and Apparatus For EUV Mask Having Diffusion Barrier - A photomask is provide. The photomask includes a substrate having a multi-layer stack disposed over the substrate. The multilayer stack has alternating first second and third layers disposed over each other, wherein the first, second and third layers are composed of first, second and third materials, respectively, and wherein at least the second layer is formed through an atomic layer deposition process. A capping layer is disposed over the multilayer stack; and an absorber layer disposed over the capping layer. A method for evaluating materials, unit processes, and process sequences for manufacturing a photomask is also provided. | 08-01-2013 |
20130209927 | Method and Apparatus For EUV Mask Having Diffusion Barrier - A photomask is provide. The photomask includes a substrate having a multi-layer stack disposed over the substrate. The multilayer stack has alternating first second and third layers disposed over each other, wherein the first, second and third layers are composed of first, second and third materials, respectively, and wherein at least the second layer is formed through an atomic layer deposition process. A capping layer is disposed over the multilayer stack; and an absorber layer disposed over the capping layer. A method for evaluating materials, unit processes, and process sequences for manufacturing a photomask is also provided. | 08-15-2013 |
20130217202 | HIGH PERFORMANCE DIELECTRIC STACK FOR DRAM CAPACITOR - A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value. | 08-22-2013 |
20130320495 | Integration of Non-Noble DRAM Electrode - A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment. | 12-05-2013 |
20130328168 | Manufacturable High-k dram mim capacitor structure - A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin (<2nm) or highly doped so that it remains amorphous after subsequent anneal treatments. A second dielectric material is formed above the first dielectric material. The second dielectric material is sufficiently thick (>3nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material. | 12-12-2013 |
20140077336 | Leakage reduction in DRAM MIM capacitors - A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer. | 03-20-2014 |
20140080282 | Leakage reduction in DRAM MIM capacitors - A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer. | 03-20-2014 |