Patent application number | Description | Published |
20090141579 | Power Up/Down Sequence Scheme for Memory Devices - A method for controlling a word line signal for a memory device during a power down process, comprising: pulling the word line signal down to a low logic state; disconnecting a current path from an external power supply to an internal power supply after the word line signal has been pulled down to the low logic state; and disconnecting a current path from an external ground voltage to an internal ground voltage after a current path from an external power supply to an internal power supply has been completely disconnected. | 06-04-2009 |
20090175099 | Single End Read Module for Register Files - A read module for register files includes at least one local I/O module coupled to a memory cell for outputting a value stored in the memory cell; and at least one global bit line driver having an input terminal coupled to the local I/O module, and a output terminal coupled to a global bit line for selectively pre-charging the global bit line at a default voltage in response to a local pre-charge signal, and outputting the value stored in the memory cell to the global bit line when the local pre-charge signal is not asserted. | 07-09-2009 |
20110199846 | Y-DECODE CONTROLLED DUAL RAIL MEMORY - An embodiment of the invention is related to a memory that includes a memory array having a plurality of memory banks, each of which includes a plurality of rows and a plurality of columns of memory cells. Each memory column includes a switch circuit providing a first voltage and a second voltage to memory cells in the column and to the pre-charge circuit associated with the column. In an application, at one particular point in time (e.g., an accessed cycle), only one column in a memory bank uses the operating voltage Ovoltage while the other N−1 columns in the same memory bank use the retention voltage Rvoltage. Other embodiments are also disclosed. | 08-18-2011 |
20110280095 | MEMORY CIRCUITS HAVING A PLURALITY OF KEEPERS - A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers. | 11-17-2011 |
20120008376 | MEMORY WITH REGULATED GROUND NODES - Some embodiments regard a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein a column of the plurality of columns includes a column ground node; at least two voltage sources configured to be selectively coupled to the column ground node; and a plurality of memory cells having a plurality of internal ground nodes electrically coupled together and to the column ground node. | 01-12-2012 |
20130155751 | MEMORY DEVICES HAVING BREAK CELLS - A representative memory device includes a cell array, at least one break cell that subdivides the cell array into bit cell arrays, and one or more power switches that are electrically coupled to the bit cell. In one embodiment, the break cell separates a connectivity of a first voltage and a second voltage between at least two bit cell arrays so that the bit cell arrays can be selectively coupled to either the first voltage or the second voltage using the power switches. The power switches control the connection of each separated bit cell array of the cell array to either the first voltage or second voltage. | 06-20-2013 |
20140043921 | METHOD OF MEMORY WITH REGULATED GROUND NODES - A method of reading data from an accessed memory cell of an accessed column of an accessed section of a memory array includes, in the accessed section, electrically coupling a first voltage source of at least three voltage sources to a corresponding column internal ground node of the accessed column; and electrically coupling the first voltage source to a corresponding column internal ground node of an un-accessed column. The memory array has at least one segment, the at least one segment has at least one section, and each section has at least one column. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches. | 02-13-2014 |
20160104525 | METHOD OF WRITING MEMORY WITH REGULATED GROUND NODES - A method of writing data to an accessed memory cell of an accessed column of an accessed section of a memory array includes, electrically coupling a first voltage source of at least three voltage sources to a column internal ground node of the accessed column; and electrically coupling the first voltage source of the at least three voltage sources to a column internal ground node of an un-accessed column of an un-accessed segment. The memory array has at least one segment. Each memory cell has an internal ground node. The at least one segment has at least one section, and each section has at least one column and at least one row. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches. | 04-14-2016 |