Patent application number | Description | Published |
20100258851 | NANOCRYSTAL MEMORIES AND METHODS OF FORMING THE SAME - Nanocrystal memories and methods of making the same are disclosed. In one embodiment, a memory device comprises a substrate, a tunneling oxide, a silicide nanocrystal floating gate, and a control oxide. The tunneling oxide is positioned upon a first surface of the substrate, the silicide nanocrystal floating gate is positioned upon the tunneling oxide, and the control oxide positioned upon the nanocrystal floating gate. | 10-14-2010 |
20130070531 | SUBSTRATE BIAS DURING PROGRAM OF NON-VOLATILE STORAGE - A programming technique which reduces program disturb in a non-volatile storage system is disclosed. A positive voltage may be applied to a substrate (e.g., p-well) during programming. Biasing the substrate may improve boosting of channels of unselected NAND strings, which may reduce program disturb. The substrate may be charged up during the programming operation, and discharged after programming. Therefore, for operations such as verify and read, the substrate may be grounded. In one embodiment, the substrate is charged just prior to applying a program pulse, then discharged prior to a program verify operation. In one embodiment, the substrate is charged while unselected word lines are ramped up to a pass voltage. The substrate bias may depend on program voltage, temperature, and/or hot count. | 03-21-2013 |
20130163340 | NON-VOLATILE STORAGE SYSTEM WITH THREE LAYER FLOATING GATE - A non-volatile storage system includes memory cells with floating gates that comprises three layers separated by two dielectric layers (an upper dielectric layer and lower dielectric layer). The dielectric layers may be an oxide layers, nitride layers, combinations of oxide and nitride, or some other suitable dielectric material. The lower dielectric layer is close to the bottom of the floating gate (near interface between floating gate and tunnel dielectric), while the upper dielectric layer is close to top of the floating gate (near interface between floating gate and inter-gate dielectric). | 06-27-2013 |
20140059405 | SOLID-STATE DRIVE RETENTION MONITOR USING REFERENCE BLOCKS - A solid-state storage retention monitor determines whether user data in a solid-state device is in need of a scrubbing operation. One or more reference blocks may be programmed with a known data pattern, wherein the reference block(s) experiences substantially similar P/E cycling, storage temperature, storage time, and other conditions as the user blocks. The reference blocks may therefore effectively represent data retention properties of the user blocks and provide information regarding whether/when a data refreshing operation is needed. | 02-27-2014 |
20140164870 | SYSTEM AND METHOD FOR LOWER PAGE DATA RECOVERY IN A SOLID STATE DRIVE - In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller performs a method that efficiently resolves the lower page corruption problem. In one embodiment, the method selects programmed lower page(s) for which paired upper page(s) have not been programmed, reads data from those selected lower page(s), corrects the read data, and reprograms the read data into those lower page(s). Since the number of lower pages in this condition is typically low (e.g., several pages in a block with hundreds or thousands of pages), this is a much more efficient method than reprogramming the entire block. In another embodiment, a similar reprogramming method is applied as a data recovery scheme in situations in which only lower pages are programmed (e.g., SLC memory, MLC memory in SLC mode, etc.). | 06-12-2014 |
20140169102 | LOG-LIKELIHOOD RATIO AND LUMPED LOG-LIKELIHOOD RATIO GENERATION FOR DATA STORAGE SYSTEMS - An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) for upper and lower pages of memory cells in MLC solid-state media. Disclosed are systems and methods for generating lumped-LLR for upper pages, wherein at least some voltage threshold reads are linked together in order to reduce the number of reads. Efficiency and reliability are thereby improved. | 06-19-2014 |
20140301142 | SYSTEMS AND METHODS OF WRITE PRECOMPENSATION TO EXTEND LIFE OF A SOLID-STATE MEMORY - Write precomensation mechanisms for non-volatile solid-state memory are disclosed. In one embodiment, programming verify voltage levels are lowered from the default levels in the early life of the solid-state memory. As memory errors increase beyond an error threshold, programming verify voltage levels are increased by one or more voltage step sizes. This programming verify voltage level increase can be performed until default levels are reached or exceeded. As a result of lowered programming verify voltage levels in the early life of the solid-state memory device, solid-state memory experiences less wear and the operational life of the memory can be extended. Disclosed write precomensation mechanisms can be used for single-level cell (SLC) and multi-level cell (MLC) memory. | 10-09-2014 |
20140359202 | READING VOLTAGE CALCULATION IN SOLID-STATE STORAGE DEVICES - An error management system for a data storage device includes adjusted reading voltage level calculation functionality. Adjusted reading voltage level calculation may be based on the generation and use of an index in which data retention characteristics of a drive are used to look-up corresponding reading voltage levels. In certain embodiments, reading voltage level calculation is based at least in part on curve-fitting procedures/algorithms, wherein curves are fitted to bit error rate data points or cumulative memory cell distributions and are solved according to one or more algorithms to determine optimal reading voltage levels. | 12-04-2014 |