Patent application number | Description | Published |
20140041827 | Heat Transfer Device Management - Techniques involving management of a heat transfer device are described. In one or more implementations, a device includes a housing, a heat-generating device disposed within the housing, and a heat transfer device disposed within the housing. The heat transfer device has a powered active cooling device. The device also includes one or more modules that are configured to adjust operation of the powered active cooling device based on a likely orientation of the heat transfer device. | 02-13-2014 |
20140094973 | SENSED SOUND LEVEL BASED FAN SPEED ADJUSTMENT - Sounds sensed by a microphone of a device include sounds from a cooling fan of the device that varies based on the speed of the cooling fan, and other sounds used by a program of the device such as voice inputs. The sound level of sounds used by the program is determined, and the speed of the fan is adjusted so that a desired cooling level is attained while keeping the fan speed low enough that the noise from the fan does not interfere with the sounds used by the program. | 04-03-2014 |
20150116928 | Centrifugal Fan with Integrated Thermal Transfer Unit - Disclosed herein are computing devices, and methods of manufacturing computing devices, that have a cooling fan and integrated thermal transfer unit. A centrifugal fan unit includes a rotatable hub, a plurality of blades disposed on the rotatable hub, and a motor coupled to the rotatable hub. The motor causes the rotatable hub to rotate about an axis such that airflow proceeds outward from the centrifugal fan unit along trajectories that are perpendicular to the axis. One or more thermal transfer units have first portions that are coupled to the one or more heat sources and second portions that collectively at least partially surround the centrifugal fan unit. | 04-30-2015 |
Patent application number | Description | Published |
20100112360 | LAYERED THERMAL INTERFACE SYSTEMS METHODS OF PRODUCTION AND USES THEREOF - A layered thermal interface system is described herein that comprises: at least one deposition layer of metal, at least one layer of thermal interface material, at least one plated layer of metal, and at least one heat spreader. Another layered thermal interface system is described herein that comprises: a silicon layer, at least one deposition layer of metal, at least one layer of thermal interface material, at least one plated layer of metal, and at least one heat spreader Methods of forming contemplated layered thermal system comprise: a) providing at least one deposition layer of metal, b) providing at least one plated layer of metal, c) providing at least one thermal interface material, and d) layering the at least one deposition layer of metal, the at least one thermal interface material, and the at least one plated layer of metal to produce the layered thermal system. Methods of forming another contemplated layered thermal system comprise: a) providing a silicon die, layer or surface, b) providing at least one deposition layer of metal, c) providing at least one plated layer of metal, d) providing at least one thermal interface material, e) providing at least one heat spreader material, and f) layering the silicon surface, the at least one deposition layer of metal, the at least one thermal interface material, the at least one plated layer of metal and the at least one heat spreader to produce the layered thermal system. | 05-06-2010 |
20100129648 | ELECTRONIC PACKAGING AND HEAT SINK BONDING ENHANCEMENTS, METHODS OF PRODUCTION AND USES THEREOF - Electronic components described herein include a heat generating component surface; a heat sink having a top surface and a bottom surface; and a thermal interface material comprising a phase change material, wherein the heat generating component surface is coupled to the bottom surface of the heat sink by the thermal interface material. Methods of forming an electronic component include: a) providing a heat-generating component surface; b) providing at least one thermal interface material; c) providing a heat sink component having a top surface and a bottom surface; d) depositing the at least one thermal interface material onto at least part of at least one of the surfaces of the heat sink component, and e) coupling the surface of the heat sink component with the thermal interface material layer with the heat generating component surface to produce the electronic component. | 05-27-2010 |
Patent application number | Description | Published |
20150088333 | Monitoring Surface Temperature of Devices - Techniques for monitoring surface temperature of devices are described. Generally, surface temperature of devices is monitored and controlled to prevent user discomfort and/or injury that may result from user contact with an excessively heated surface. In at least some embodiments, temperature of an external surface of the device is indirectly monitored. For instance, a temperature sensor is positioned at an internal location in a device that has a known temperature relationship to a temperature of an external surface of the device. Alternatively or additionally, a temperature of an external surface of a device may be directly detected. In at least some embodiments, when a temperature of an external surface of a device is determined to reach or exceed a threshold temperature, procedures can be implemented to reduce the temperature of the external surface and/or prevent further heating of the external surface. | 03-26-2015 |
20150286256 | Micro-Hole Vents for Device Ventilation Systems - Micro-hole vents for device ventilation systems are described herein that may be formed as a plurality of micro-holes that are invisible to unaided human eyes. The micro-holes are configured to blend into the housing for a computing device such that the holes are substantially concealed from users of the computing device. A micro-hole vent may be aligned with a blower for a ventilation system to enable air intake through the corresponding micro-holes for cooling of components within the housing. In addition or alternatively, one or more exhaust vents for the ventilation system may also be configured as micro-hole vents. Each micro-hole vent may have many, very small holes for sufficient air flow. For example, micro-holes having diameters of about fifty to two hundred microns may be arranged in a pattern with a coverage in a range of about twelve thousand to fifty thousand holes per square inch. | 10-08-2015 |
20150331461 | Computing Device having a Spectrally Selective Radiation Emission Device - A computing device having a spectrally selective radiation emission device is described. In one or more implementations, an apparatus includes a housing, one or more electrical components disposed within the housing, and a spectrally selective radiation emission device. The one or more electrical components are configured to generate heat during operation. The spectrally selective radiation emission device is disposed on the housing and configured to emit radiation when heated by the one or more electrical components at one or more wavelengths of electromagnetic energy and reflect radiation at one or more other wavelengths of electromagnetic energy. | 11-19-2015 |
20160077558 | Uniform Flow Heat Sink - A uniform flow heat sink is described that is configured to employ variable spacing for air flow channels to account for non-uniformities in air flow due to arrangements of components within a housing of a computing device. Non-uniformities may be ascertained by analysis of an air flow profile for a computing device to detect regions of high and low flow. Air flow rates for the computing device may be balanced by configuring air flow channel spacing for the heat sink to vary around a perimeter of the heat sink and account for the ascertained non-uniformities. Air flow channel spacing may be controlled by changing the concentration, spacing, pitch, positioning and/or other characteristics of heat transfer surfaces associated with the heat sink. Generally, air flow channel spacing is increased in areas of high system impedance and decreased in areas of low system impedance to increase uniformity of flow. | 03-17-2016 |
Patent application number | Description | Published |
20080315955 | CLASS L AMPLIFIER - A new Class L amplifier which dynamically switches between multiple pairs of power rails, and has the ability to select the most advantageous combination of rails for the minimization of power dissipation in the amplifier. In one embodiment, a bridged amplifier system includes two Class L amplifiers to drive a load. | 12-25-2008 |
20110129098 | ACTIVE NOISE CANCELLATION - This document discusses, among other things, systems and methods for active noise cancellation. One example system includes a digital ANC circuit configured to receive first audio information from a first microphone and to produce an a digital anti-noise signal configured to attenuate noise sensed by the first microphone; an analog ANC circuit configured to receive second audio information from a second microphone and to produce an analog anti-noise signal configured to attenuate noise sensed by the second microphone; and wherein the system is configured to receive an intended audio signal and to provide an output signal for a speaker using the intended audio signal, the analog anti-noise signal, and the digital anti-noise signal. | 06-02-2011 |
20110148385 | SELECTIVELY ACTIVATED THREE-STATE CHARGE PUMP - This document discusses, among other things, a device for providing a DC output voltage, including a first output voltage and a second output voltage, from an input voltage. The device can include a first voltage regulator configured to provide the first output voltage when the input voltage is below a threshold voltage, and a charge pump configured to provide the second output voltage from the first output voltage in a two-state mode when the input voltage is below the threshold voltage, and to provide the first output voltage and the second output voltage in a three-state mode when the input voltage is above the threshold voltage. | 06-23-2011 |
20110148510 | REDUCED CURRENT CHARGE PUMP - This document discusses, among other things, a charge pump having a plurality of switching devices, coupled in parallel, and configured to selectively provide a variable available drive current for a capacitor using a comparison of an output voltage to at least one reference voltage. | 06-23-2011 |
20130082771 | RESOURCE POOLING AMPLIFIER - A new type of amplifier, herein designated a resource pooling amplifier, involves extended usage of one or more inductors that is implemented by sharing. The sharing is either by switching the inductor or inductors among more than one load terminal at the same time (e.g., a bridged configuration or two different loads terminals with different polarity requirements) or by using the inductor or inductors for more than one purpose at different times. The inductor or inductors may be time shared such as by allocating different phases of a clock. The inductor or inductors may also be shared by monitoring load requirements and using the inductor or inductors only when needed (leaving other inductor cycles for other loads). In addition, inductor sharing may be implemented during different application requirements such as if two or more loads are not needed at the same time in a system. These types of sharing may be combined. | 04-04-2013 |
Patent application number | Description | Published |
20090019267 | Method, System, and Apparatus for Dynamic Reconfiguration of Resources - A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware. | 01-15-2009 |
20090024715 | Method, System, and Apparatus for Dynamic Reconfiguration of Resources - A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware. | 01-22-2009 |
20090055600 | Method, System, and Apparatus for Dynamic Reconfiguration of Resources - A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware. | 02-26-2009 |
20100332767 | Controllably Exiting An Unknown State Of A Cache Coherency Directory - In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message is sent to at least one other caching agent to invalidate information in a cache location of the other caching agent corresponding to the location of the read request, to enable setting of the directory entry into a known state. Other embodiments are described and claimed. | 12-30-2010 |
20110078384 | MEMORY MIRRORING AND MIGRATION AT HOME AGENT - Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed. | 03-31-2011 |
20110078492 | HOME AGENT DATA AND MEMORY MANAGEMENT - Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed. | 03-31-2011 |
20140173206 | Power Gating A Portion Of A Cache Memory - In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed. | 06-19-2014 |
20140173207 | Power Gating A Portion Of A Cache Memory - In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed. | 06-19-2014 |
20140189239 | PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES - A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed. | 07-03-2014 |
20160077970 | Virtual Shared Cache Mechanism in a Processing Device - In accordance with embodiments disclosed herein, there is provided systems and methods for providing a virtual shared cache mechanism. A processing device includes a plurality of clusters allocated into a virtual private shared cache. Each of the clusters includes a plurality of cores and a plurality of cache slices co-located within the plurality of cores. The processing device also includes a virtual shared cache including the plurality of clusters such that the cache data in the plurality of cache slices is shared among the plurality of clusters. | 03-17-2016 |
Patent application number | Description | Published |
20100179091 | Treatment of Conditions Related to Shock - Techniques are disclosed for prevention or treatment of physiological shock by administering a specific therapeutic agent or combination of therapeutic agents, which is/are able to use smaller volumes of reagent to achieve complete inhibition, than other previously described techniques. | 07-15-2010 |
20100303799 | Treatment of Conditions Related to Shock - Techniques are disclosed for prevention or treatment of physiological shock by administering a specific therapeutic agent, which is able to use smaller volumes of reagent to achieve complete inhibition, than other previously described techniques. | 12-02-2010 |
20110039781 | Treatment of Conditions Related to Cecal Ligation Shock - Techniques, methods and lavages are disclosed for prevention or treatment of shock, particularly cecal ligation or cecal inoculation shock, by administering a specific therapeutic agent, which is able to use smaller volumes of reagent to achieve partial to complete inhibition, than other previously described techniques. The agent includes a combination of enzyme inhibitor, cytotoxic lipid binding protein, and antibiotic. | 02-17-2011 |
20120309693 | Methods to Accelerate Tissue and Wound Healing Rates and Reduce Swelling and Scar Formation - The present disclosure serves to reduce the healing time of tissue wounds, including those formed during surgery, whether necessary or elective (including cosmetic surgery), by providing a therapeutic dose of a pancreatic enzyme inhibitor. | 12-06-2012 |
20130231309 | TREATMENT OF INFLAMMATION AND ORGAN DYSFUNCTION - Compositions and methods are disclosed for decreasing the amount and activity of matrix-degrading metalloproteinases (MMPs) in and around cells. The compositions and methods are useful for treating and/or preventing symptoms of diseases including but not limited to Hypertension, Type II Diabetes, and Metabolic Syndrome X. Such treatment is effected by normalizing the blood plasma's protease activity, reducing blood pressure, preventing membrane receptor cleavage, and reducing the levels of insulin resistance and oxygen free radicals in the blood stream. | 09-05-2013 |
20140018293 | MINIMIZING INTESTINAL DYSFUNCTION - Techniques are discloded for treating or reducing sumptoms associated with abdominal dysfunction or ileus following surgery or other abdominal episode by treating the area with a combination of one or more protease, antibacterial compound, and inflammatory lipid mediator. | 01-16-2014 |