# Deepak K. Singh, Apex US

## Deepak K. Singh, Apex, NC US

Patent application number | Description | Published |
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20090055122 | On-Chip Frequency Response Measurement - A method and circuit are provided for measuring frequency response performance of an integrated circuit by providing a pulse having a rising edge and a falling edge where the pulse is provided to a plurality of serially connected components. The number of these components which have propagated the leading edge of the pulse before the occurrence of the falling edge provide a numeric indication of the circuit's frequency response and performance. | 02-26-2009 |

20090055454 | Half Width Counting Leading Zero Circuit - A circuit and method are provided for storing a data word in a latch and determining the number of consecutive equal value bits within the data word. The data word consists of bits stored in unique bit positions and having a least significant bit position and a most significant bit position. The data word is examined to determine the number of consecutive bits having the same numeric value. The invention first corrects for any single bit anomaly within the consecutive equal value sequence, counts the number of consecutive bits having this equal value using logic that examines only every other bit position of the stored data word and provides a numeric value representing this number of consecutive equal value bits. | 02-26-2009 |

20090055456 | Data Correction Circuit - A circuit and method are provided for correcting binary values in a data word having N bit positions where the circuit includes several assemblies, each for a unique data word bit position, where each assembly includes a first logic circuit connected to its unique data word bid and an adjacent data word bit to provide a first output bit and a second logic circuit connected to receive the first output bit and a different adjacent bit of the data word to provide a second output bit representing a corrected value of the unique bit. | 02-26-2009 |

20100332875 | Fan Speed Control from Thermal Diode Measurement - Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. A method is provided for controlling the speed of a cooling fan provided to cool an integrated circuit in which includes the steps of receiving a voltage from a thermal diode, addressing a table of digital temperatures by incrementing the address of the table entries every clock cycle of a circuit clock, converting the addressed data to a second voltage representing temperature, comparing the first voltage to the second voltage, providing a resulting temperature when both the first and second voltages are equal, and adjusting the fan speed accordingly. | 12-30-2010 |

20120036172 | Expanded Scope Incrementor - An incrementor circuit and method for incrementing is provided that computes an output data word by increasing an input data word magnitude by one of several integer values. The incrementor circuit includes a mode increment signal circuit providing a designation of one of the integer values for increasing the input data word magnitude. A single constant incrementor is connected to the mode increment signal circuit and the input data word and provides an intermediate sum by selectively adding a constant to the input data word. A multiplex circuit logically combines selected input data word bit position values with the mode increment signal circuit designation forming logical bit position values and directs selected input data word bit position values, selected logical bit position values, and selected bit position values of the intermediate sum to form the output data word. | 02-09-2012 |

20130290393 | Expanded Scope Incrementer - An incrementor circuit and method for incrementing is provided that computes an output data word by increasing an input data word magnitude by one of several integer values. The incrementor circuit includes a mode increment signal circuit providing a designation of one of the integer values for increasing the input data word magnitude. A single constant incrementor is connected to the mode increment signal circuit and the input data word and provides an intermediate sum by selectively adding a constant to the input data word. A multiplex circuit logically combines selected input data word bit position values with the mode increment signal circuit designation forming logical bit position values and directs selected input data word bit position values, selected logical bit position values, and selected bit position values of the intermediate sum to form the output data word. | 10-31-2013 |

20130332788 | HALF WIDTH COUNTING LEADING ZERO CIRCUIT USING COMPARATORS - A circuit and method are provided for providing a value representing the number of leading zero bits in an input data word. The input data word contains random data. The input data word is logically divided into odd and even bit positions. The circuit includes a first comparator circuit comparing data in the odd bit positions to data in the even bit positions. The circuit further includes a second comparator circuit comparing the data in the odd bit positions to a result of a logical operation performed on the data in the odd and even bit positions. The circuit further includes a half-width leading zero counting circuit that provides the value representing the number of leading zero bits in the input data word. The comparator circuits provide a correction bit value concatenated to the value. | 12-12-2013 |

20140358979 | GENERATING A FAST 3x MULTIPLAND TERM FOR RADIX-8 BOOTH MULTIPLICATION - A 3× circuit for partial product generation used in a radix-8 multiplier receiving only a single multiplicand input. Rather than providing 2-inputs to the adder (a 2× of multiplicand and the multiplicand itself), the new 3× circuit uses the multiplicand as the only input. Thus, in terms of connections at the multiplier circuit level, only one bus is required to connect to the input of the new 3× circuit. The 3× generation adder circuit further operates at a reduced number of logic levels and speeds up the critical path by taking advantage of the repetition and fixed spatial separation of the bits for the adder inputs. | 12-04-2014 |