Patent application number | Description | Published |
20130295711 | SELF-POWERED INTEGRATED CIRCUIT WITH MULTI-JUNCTION PHOTOVOLTAIC CELL - A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a multiple photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the multiple photovoltaic cell portion. | 11-07-2013 |
20150294895 | LOCALIZED REGION OF ISOLATED SILICON OVER DIELECTRIC MESA - An integrated circuit is formed by forming an isolation mesa over a single crystal substrate which includes silicon, and forming a first epitaxial layer on the substrate by a selective epitaxial process so that a top surface of the first epitaxial layer is coplanar with the top surface of the isolation mesa. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on the first epitaxial layer and non-crystalline silicon-based material on the isolation mesa. A cap layer is formed over the second epitaxial layer, and a radiantly-induced recrystallization process causes the non-crystalline silicon-based material to form single-crystalline semiconductor over the isolation mesa. | 10-15-2015 |
20150294901 | LOCALIZED REGION OF ISOLATED SILICON OVER RECESSED DIELECTRIC LAYER - An integrated circuit is formed by forming an isolation recess in a single crystal substrate which includes silicon, filling the isolation recess with isolation dielectric material, and planarizing the isolation dielectric material to be coplanar with the top surface of the substrate to form a buried isolation layer. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on exposed areas of the substrate and polycrystalline or amorphous silicon-based material on the buried isolation layer. A cap layer is formed over the epitaxial silicon-based material, and a radiantly-induced recrystallization process causes the polycrystalline or amorphous silicon-based material to form single-crystalline semiconductor over the buried isolation layer. | 10-15-2015 |
20150294902 | ISOLATED SEMICONDUCTOR LAYER IN BULK WAFER BY LOCALIZED SILICON EPITAXIAL SEED FORMATION - An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer. | 10-15-2015 |
20150294983 | ISOLATED SEMICONDUCTOR LAYER OVER BURIED ISOLATION LAYER - An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate. | 10-15-2015 |
20150349021 | CMOS-BASED THERMOELECTRIC DEVICE WITH REDUCED ELECTRICAL RESISTANCE - An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×10 | 12-03-2015 |
20150349022 | CMOS-BASED THERMOPILE WITH REDUCED THERMAL CONDUCTANCE - An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches. | 12-03-2015 |
20150349023 | CMOS COMPATIBLE THERMOPILE WITH LOW IMPEDANCE CONTACT - An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors. | 12-03-2015 |
Patent application number | Description | Published |
20110024131 | METHOD FOR RECOVERING OIL FROM AN OIL WELL - In a method for optimizing gas lift operations in the production of crude oil, a surfactant is injected into the an oil well such that the surface tension between a lift gas and the formation fluid being produced is reduced and/or a lift gas-formation fluid foam is formed. The reduction in surface tension and/or foam formation increases the efficiency of the lift gas for lifting the formation fluid to the surface. The surfactant is a silicone resin which may be combined with other surfactants, in some embodiments. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 02-03-2011 |
20150057196 | AQUEOUS DOWNHOLE FLUIDS HAVING CHARGED NANO-PARTICLES AND POLYMERS - Charged nanoparticles may be added to an aqueous downhole fluid having polymers therein where the charged nanoparticles may crosslink at least a portion of the polymers. The polymers may be or include, but are not limited to polyacrylamide, xanthan, guar, polyacrylic acid, poly 2-acrylamido-2-methyl-1-propane sulfonic acid (AMPS), polyethylene oxide, polypropylene oxide, or combinations thereof. The polymers may be homopolymers, copolymers, terpolymers, or combinations thereof. The charged nanoparticles may be or include, but are not limited to clay nanoparticles, modified nanoparticles, or combinations thereof. The aqueous downhole fluid may be or include, but is not limited to fracturing fluids, injection fluids, and combinations thereof for performing a fracturing operation, an injection operation, another enhanced oil recovery operation, and the like. | 02-26-2015 |
Patent application number | Description | Published |
20090027213 | Perishable product electronic label including time and temerature measurement - An electronic assembly may be contained in a label that performs time-temperature integration (TTI) and indicates that time and/or temperature levels have been reached that may compromise the quality, shelf life, or safety of the item to which the label is affixed. The label may be used on a wide variety of objects that require careful handling in terms of temperature and/or time elapsed before use. The labeling system includes circuitry that measures and calculates, and indictor(s) that signal that the time has come for discounted sale, and, later, that the time has come for disposal rather than sale. Optionally, the circuitry may act as an “over-temperature alarm” system, to measure, calculate, and indicate when a one-time temperature violation has occurred that is of such a magnitude that the item is immediately considered compromised or spoiled. The label may take the form of a flexible, disposable label that is typically powered by a small battery. Methods may include providing a temperature-variable oscillator or time-base, counting cycles of said oscillator within a logic circuit to determine when one or more preset total cycle counts is/are reached, and signaling when said total cycle count(s) is/are reached. Extra sensing, time-keeping, memory storage, and/or communication interface circuits may be incorporated to augment the electronic assembly's and method's capabilities. | 01-29-2009 |
20120179374 | ENVIRONMENTAL SENSING AND COMMUNICATION - One apparatus embodiment includes an electronic assembly, equipped to sense one or more changes in an environmental condition. The assembly includes a logic circuit coupled to: one or more environmental sensors, memory that provides data storage, and a wireless communicator. The logic circuit is configured to perform time measurement, perform environmental measurement with the one or more environmental sensors, store time-stamped environmental data in the memory, and communicate with particular other electronic assemblies, equipped to sense one or more changes in an environmental condition, via the wireless communicator. The logic circuit is also coupled to a power source that provides power to at least one of the logic circuit and the wireless communicator. | 07-12-2012 |
20140104076 | ENVIRONMENTAL SENSING AND COMMUNICATION - One apparatus embodiment includes an electronic assembly, equipped to sense one or more changes in an environmental condition. The assembly includes a logic circuit coupled to: one or more environmental sensors, memory that provides data storage, and a wireless communicator. The logic circuit is configured to perform time measurement, perform environmental measurement with the one or more environmental sensors, store time-stamped environmental data in the memory, and communicate with particular other electronic assemblies, equipped to sense one or more changes in an environmental condition, via the wireless communicator. The logic circuit is also coupled to a power source that provides power to at least one of the logic circuit and the wireless communicator. | 04-17-2014 |