Patent application number | Description | Published |
20100027564 | Method, Apparatus, And System For Idle State Definition For Power Management - A predetermined network packet is utilized for power reduction in either or both of a transmitter and receiver when information is not needed. Upon detection of the predetermined network packet type, various portions of the transmitter and/or receiver may be clock gated or powered down. | 02-04-2010 |
20100098101 | PACKET FORMAT FOR A DISTRIBUTED SYSTEM - A method is provided for transmitting a packet including information describing a bus transaction to be executed at a remote device. A bus transaction is detected on a first bus and a network packet is generated for transmission over a network. The network packet includes an opcode describing the type of bus transaction. One or more control signals of the bus transaction map directly to one or more bits of the opcode to simplify decoding or converting of the bus transaction to the opcode. The packet is transmitted to a remote device and the bus transaction is then replayed at a second bus. In addition, the packet includes a data field having a size that is a multiple of a cache line size. The packet includes separate CRCs for the data and header. The packet also includes a transaction ID to support split transactions over the network. Also, fields in the packet header are provided in a particular order to improve switching efficiency. | 04-22-2010 |
20110176431 | PHYSICAL LAYER LOOPBACK - In some embodiments, a chip comprises control circuitry to provide inband signals, inband output ports, and transmitters to transmit the inband signals to the inband output ports. The control circuitry selectively includes loopback initiating commands in the inband signals. Other embodiments are described and claimed. | 07-21-2011 |
20120047305 | PACKET FORMAT FOR A DISTRIBUTED SYSTEM - A method is provided for transmitting a packet including information describing a bus transaction to be executed at a remote device. A bus transaction is detected on a first bus and a network packet is generated for transmission over a network. The network packet includes an opcode describing the type of bus transaction. One or more control signals of the bus transaction map directly to one or more bits of the opcode to simplify decoding or converting of the bus transaction to the opcode. The packet is transmitted to a remote device and the bus transaction is then replayed at a second bus. In addition, the packet includes a data field having a size that is a multiple of a cache line size. The packet includes separate CRCs for the data and header. The packet also includes a transaction ID to support split transactions over the network. Also, fields in the packet header are provided in a particular order to improve switching efficiency. | 02-23-2012 |
20130114420 | PHYSICAL LAYER LOOPBACK - In some embodiments, a chip comprises control circuitry to provide inband signals, inband output ports, and transmitters to transmit the inband signals to the inband output ports. The control circuitry selectively includes loopback initiating commands in the inband signals. Other embodiments are described and claimed. | 05-09-2013 |
20140156892 | METHOD, SYSTEM, AND APPARATUS FOR LINK LATENCY MANAGEMENT - A link latency management for a high-speed point-to-point network (pTp) is described The link latency management facilitates calculating latency of a serial interface by tracking a round trip delay of a header that contains latency information. Therefore, the link latency management facilitates testers, logic analyzers, or test devices to accurately measure link latency for a point-to-point architecture utilizing a serial interface. | 06-05-2014 |
20150074440 | LINK POWER SAVINGS WITH STATE RETENTION - Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed. | 03-12-2015 |
20150178092 | HIERARCHICAL AND PARALLEL PARTITION NETWORKS - In accordance with the present description, provided are hierarchical and parallel partition networks which include a plurality of parallel partition packet networks for interconnecting components on one or more integrated circuit dies. In one embodiment, each parallel partition packet network is independent of the other parallel partition packet networks and has a unit level switch at a unit hierarchical level. In another aspect, each parallel partition packet network has a unit-to-unit level switch at a unit-to-unit hierarchical level. Other aspects are described herein. | 06-25-2015 |