Patent application number | Description | Published |
20110243134 | Data Frame Forwarding Using a Distributed Virtual Bridge - Systems and methods to forward data frames are provided. A particular method may include receiving a data frame at a distributed virtual bridge. The distributed virtual bridge includes a first bridge element coupled to a first server computer and a second bridge element coupled to the first bridge element and to a second server computer. The distributed virtual bridge further includes a controlling bridge coupled to the first bridge element and to the second bridge element. The controlling bridge includes a global forwarding table. The data frame is forwarded from the first bridge element to the second bridge element of the distributed virtual bridge using address data associated with the data frame. A logical network associated with the frame may additionally be used to forward the data frame. | 10-06-2011 |
20110243146 | Data Frame Forwarding Using a Multitiered Distributed Virtual Bridge Hierarchy - Systems and methods to forward data frames are provided. A particular method may include evaluating address data of a first data frame at a first virtual bridge coupled to a first virtual machine of a first server computer of a plurality of server computers. Based upon the evaluation at the first virtual bridge, the first data frame may be forwarded to a second virtual bridge associated with an adapter that is coupled to the first virtual machine. The address data of the first data frame may be evaluated at the second virtual bridge. Based upon the evaluation, the data frame may be forwarded to a third virtual bridge configured to forward the data frame based upon the address data to a second server computer of the plurality of server computers. | 10-06-2011 |
20110252167 | PHYSICAL TO HIERARCHICAL BUS TRANSLATION - In an embodiment, a translation of a physical bus number to a hierarchical bus number is written to a south chip. The south chip receives a configuration write command that comprises a physical bus number. The south chip sends the configuration write command to a device via the bus identified by the physical bus number, and the device stores the physical bus number in the device. In response to a received message from a device that comprises the physical bus number, the south chip replaces the physical bus number in the message with the hierarchical bus number. The south chip sends the message to a north chip via a point-to-point serial link. Both the physical bus number and the hierarchical bus number identify a bus with which the device connects to a bridge in the south chip. | 10-13-2011 |
20110252170 | HIERARCHICAL TO PHYSICAL BUS TRANSLATION - In an embodiment, a translation of a hierarchical bus number to a physical bus number and a bridge identifier of a bridge are written to a north chip. A request is received that comprises an identifier of a destination. A determination is made that the identifier comprises the hierarchical bus number. In response to the determination, the identifier of the destination is replaced in the request with the physical bus number and the bridge identifier. The request is sent to the bridge identified by the bridge identifier. A south chip comprises the bridge, and the south chip is connected to the north chip via a point-to-point serial link. The physical bus number identifies a bus that connects the bridge to a device. The request comprises a configuration write request that requests a write of data to the device. | 10-13-2011 |
20110252173 | TRANSLATING A REQUESTER IDENTIFIER TO A CHIP IDENTIFIER - In an embodiment a translation of RID (requester identifier) ranges to identifiers of north chips is stored into a south chip. A command that comprises a command RID is received at the south chip from a device. In response, a RID range is determined that encompasses the command RID, and a north chip identifier is found that is assigned a virtual function identified by the command RID. The command is sent from the south chip to the north chip identified by the north chip identifier. The translation comprises a RID compare value and a RID mask. A determination is made that the RID range encompasses the command RID by performing a logical-and operation on the command RID and the RID mask and comparing a result of the logical-and operation to the RID compare value. | 10-13-2011 |
20110252174 | HIERARCHICAL TO PHYSICAL MEMORY MAPPED INPUT/OUTPUT TRANSLATION - In an embodiment, a translation of a hierarchical MMIO address range to a physical MMIO address range and an identifier of a bridge in a south chip are written to a north chip. A transaction is received that comprises a hierarchical MMIO address. The hierarchical MMIO address that is within the hierarchical MMIO address range is replaced in the transaction with the identifier of the bridge and with a physical MMIO address that is within the physical MMIO address range in the south chip. The transaction is sent to the device that is connected to the bridge in the south chip. The physical MMIO address range specifies a range of physical MMIO addresses in memory in the device. | 10-13-2011 |
20110258340 | Distributed Virtual Bridge Management - Systems and methods to forward data frames are described. A particular method may include receiving a data frame at a switch of a plurality of networked switches coupled to a plurality of server computers. The data frame may be forwarded from a controlling bridge coupled to the plurality of networked switches. The data frame may be determined to include management data, and an operating parameter of the switch may be modified. | 10-20-2011 |
20110258641 | Remote Adapter Configuration - Systems and methods to remotely configure adapters are described. A particular method may include generating a management frame at a controlling bridge. The management frame may include instructions to configure an operating parameter of the adapter. The management frame may be communicated to a bridge element of a plurality of interconnected bridge elements in communication with the controlling bridge. The bridge element may be coupled to the adapter, and the operating parameter of the adapter may be configured. | 10-20-2011 |
20110264610 | Address Data Learning and Registration Within a Distributed Virtual Bridge - Systems and methods to forward data frames are provided. A particular apparatus may include a plurality of server computers and a distributed virtual bridge. The distributed virtual bridge may include a plurality of bridge elements coupled to the plurality of server computers and configured to forward a data frame between the plurality of server computers. The plurality of bridge elements may further be configured to automatically learn address data associated with the data frame. A controlling bridge may be coupled to the plurality of bridge elements. The controlling bridge may include a global forwarding table that is automatically updated to include the address data and is accessible to the plurality of bridge elements. | 10-27-2011 |
20110276779 | MEMORY MAPPED INPUT/OUTPUT BUS ADDRESS RANGE TRANSLATION - In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge. | 11-10-2011 |
20110320671 | MOVING OWNERSHIP OF A DEVICE BETWEEN COMPUTE ELEMENTS - In an embodiment, a command is received that requests movement of ownership of a target device from an origin compute element to a destination compute element. From the origin compute element, a translation of a virtual bridge identifier to a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range is removed. To the destination compute element, a translation of the target virtual bridge identifier to a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range is added. From a south chip that comprises the target virtual bridge, a translation of the target virtual bridge identifier to an identifier of the origin compute element is removed. To the south chip, a translation of the target virtual bridge identifier to an identifier of the destination compute element is added. | 12-29-2011 |
20120017022 | REGISTER ACCESS IN DISTRIBUTED VIRTUAL BRIDGE ENVIRONMENT - Systems and methods to perform a register access are described. A particular method includes receiving a data frame at a bridge element of a plurality of bridge elements in communication with a plurality of server computers. The data frame may include a register access request and may be forwarded from a controlling bridge in communication with the plurality of bridge elements. A register may be accessed and execution of the register access request may be initiated in response to receiving the data frame. | 01-19-2012 |
20130010419 | REDUCING IMPACT OF REPAIR ACTIONS FOLLOWING A SWITCH FAILURE IN A SWITCH FABRIC - Techniques are disclosed for reducing impact of a switch failure and/or a repair action in a switch fabric. In one embodiment, a server system is provided that includes a first interposer card that operatively connects one or more server cards to a midplane. The first interposer card may include a switch module that switches network traffic for the one or more server cards. The first interposer card may be hot-swappable from the midplane, and the one or more server cards may be hot-swappable from the first interposer card. The server system may further include an interconnect between the first interposer card and a second interposer card. | 01-10-2013 |
20130010639 | SWITCH FABRIC MANAGEMENT - Techniques are disclosed for managing a switch fabric. In one embodiment, a server system is provided that includes a midplane, one or more server cards, switch modules and a management controller. The midplane may include a fabric interconnect for a switch fabric. The one or more server cards and the switch modules may be operatively connected to the midplane. The switch modules may be configured to switch network traffic for the one or more server cards. The management controller may be configured to manage the switch modules via the fabric interconnect. | 01-10-2013 |
20130013956 | REDUCING IMPACT OF A REPAIR ACTION IN A SWITCH FABRIC - Techniques are disclosed for reducing impact of a repair action in a switch fabric. In one embodiment, a server system is provided that includes a first interposer card that operatively connects one or more server cards to a midplane. The first interposer card may include a switch module that switches network traffic for the one or more server cards. The first interposer card may be hot-swappable from the midplane, and the one or more server cards may be hot-swappable from the first interposer card. | 01-10-2013 |
20130013957 | REDUCING IMPACT OF A SWITCH FAILURE IN A SWITCH FABRIC VIA SWITCH CARDS - Techniques are disclosed for reducing impact of a switch failure in a switch fabric. In one embodiment, a server system is provided that includes a midplane, one or more server cards and one or more switch cards. The midplane may include a fabric interconnect for a switch fabric. The one or more server cards may be coupled with the midplane, where each server card is hot-swappable from the midplane. The one or more switch cards may also be coupled with the midplane, where each switch card is also hot-swappable from the midplane. Each switch card includes one or more switch modules, and each switch module is configured to switch network traffic for at least one server card. | 01-10-2013 |
20130094348 | SWITCH FABRIC MANAGEMENT - Techniques are disclosed for managing a switch fabric. In one embodiment, a server system is provided that includes a midplane, one or more server cards, switch modules and a management controller. The midplane may include a fabric interconnect for a switch fabric. The one or more server cards and the switch modules may be operatively connected to the midplane. The switch modules may be configured to switch network traffic for the one or more server cards. The management controller may be configured to manage the switch modules via the fabric interconnect. | 04-18-2013 |
20130094351 | REDUCING IMPACT OF A SWITCH FAILURE IN A SWITCH FABRIC VIA SWITCH CARDS - Techniques are disclosed for reducing impact of a switch failure in a switch fabric. In one embodiment, a server system is provided that includes a midplane, one or more server cards and one or more switch cards. The midplane may include a fabric interconnect for a switch fabric. The one or more server cards may be coupled with the midplane, where each server card is hot-swappable from the midplane. The one or more switch cards may also be coupled with the midplane, where each switch card is also hot-swappable from the midplane. Each switch card includes one or more switch modules, and each switch module is configured to switch network traffic for at least one server card. | 04-18-2013 |
20130100799 | REDUCING IMPACT OF REPAIR ACTIONS FOLLOWING A SWITCH FAILURE IN A SWITCH FABRIC - Techniques are disclosed for reducing impact of a switch failure and/or a repair action in a switch fabric. In one embodiment, a server system is provided that includes a first interposer card that operatively connects one or more server cards to a midplane. The first interposer card may include a switch module that switches network traffic for the one or more server cards. The first interposer card may be hot-swappable from the midplane, and the one or more server cards may be hot-swappable from the first interposer card. The server system may further include an interconnect between the first interposer card and a second interposer card. | 04-25-2013 |
20130103329 | REDUCING IMPACT OF A REPAIR ACTION IN A SWITCH FABRIC - Techniques are disclosed for reducing impact of a repair action in a switch fabric. In one embodiment, a server system is provided that includes a first interposer card that operatively connects one or more server cards to a midplane. The first interposer card may include a switch module that switches network traffic for the one or more server cards. The first interposer card may be hot-swappable from the midplane, and the one or more server cards may be hot-swappable from the first interposer card. | 04-25-2013 |
20130117469 | REGISTER ACCESS IN DISTRIBUTED VIRTUAL BRIDGE ENVIRONMENT - Systems and methods to perform a register access are described. A particular method includes receiving a data frame at a bridge element of a plurality of bridge elements in communication with a plurality of server computers. The data frame may include a register access request and may be forwarded from a controlling bridge in communication with the plurality of bridge elements. A register may be accessed and execution of the register access request may be initiated in response to receiving the data frame. | 05-09-2013 |
20130142196 | DISTRIBUTING FUNCTIONS IN A DISTRIBUTED AND EMBEDDED ENVIRONMENT - The different switch modules making up a distributed virtual switch may route configuration commands for hardware resources to different modules within the distributed switch using a distribution and routing layer. At least one of the switch modules maintains a routing table that defines which switch modules are responsible for which hardware resources. The switch module uses the routing tables to forward the commands on the distribution and routing layer to the responsible switch module which then ensures that the relevant hardware resources are configured. | 06-06-2013 |
20130142202 | DISTRIBUTING FUNCTIONS IN A DISTRIBUTED AND EMBEDDED ENVIRONMENT - The different switch modules making up a distributed virtual switch may route configuration commands for hardware resources to different modules within the distributed switch using a distribution and routing layer. At least one of the switch modules maintains a routing table that defines which switch modules are responsible for which hardware resources. The switch module uses the routing tables to forward the commands on the distribution and routing layer to the responsible switch module which then ensures that the relevant hardware resources are configured. | 06-06-2013 |
20130155837 | Selecting a Master Processor From an Ambiguous Peer Group - A distributed switch may include a plurality of special-purpose processors that control the different functions of the switch. To enable some special services, however, the distributed switch may need one of these processors to perform the role of a master. When a processor is powered on, the processor may publish a corresponding unique ID. Before electing the master, the special-purpose processors may use a discovery process to identify the network topology of the switch and evaluate the published IDs to determine which processor should be the master. If all the processors nominate the same master processor, then that processor is elected as the master and may finish configuring the distributed switch to enable the special services. | 06-20-2013 |
20130155841 | SELECTING A MASTER PROCESSOR FROM AN AMBIGUOUS PEER GROUP - A distributed switch may include a plurality of special-purpose processors that control the different functions of the switch. To enable some special services, however, the distributed switch may need one of these processors to perform the role of a master. When a processor is powered on, the processor may publish a corresponding unique ID. Before electing the master, the special-purpose processors may use a discovery process to identify the network topology of the switch and evaluate the published IDs to determine which processor should be the master. If all the processors nominate the same master processor, then that processor is elected as the master and may finish configuring the distributed switch to enable the special services. | 06-20-2013 |
20130208721 | PACKET ROUTING WITH ANALYSIS ASSIST FOR EMBEDDED APPLICATIONS SHARING A SINGLE NETWORK INTERFACE OVER MULTIPLE VIRTUAL NETWORKS - Techniques are provided for packet routing in a distributed network switch. The distributed network switch includes multiple switch modules operatively connected to one another, and each switch module includes multiple bridge elements and a management controller. In one embodiment, a shared interface routing (SIR) framework is provided that includes an analysis and bifurcation layer, at least one packet interface, and an analysis assist layer. A packet is received over a first logical network and via a physical port, the packet being destined for at least a first application executing on the management controller. The analysis assist layer analyzes the packet to determine a reason code to assign to the packet. The analysis and bifurcation layer then analyzes the packet based at least in part on the reason code. | 08-15-2013 |
20130208722 | PACKET ROUTING WITH ANALYSIS ASSIST FOR EMBEDDED APPLICATIONS SHARING A SINGLE NETWORK INTERFACE OVER MULTIPLE VIRTUAL NETWORKS - Techniques are provided for packet routing in a distributed network switch. The distributed network switch includes multiple switch modules operatively connected to one another, and each switch module includes multiple bridge elements and a management controller. In one embodiment, a shared interface routing (SIR) framework is provided that includes an analysis and bifurcation layer, at least one packet interface, and an analysis assist layer. A packet is received over a first logical network and via a physical port, the packet being destined for at least a first application executing on the management controller. The analysis assist layer analyzes the packet to determine a reason code to assign to the packet. The analysis and bifurcation layer then analyzes the packet based at least in part on the reason code. | 08-15-2013 |
20130208726 | PACKET ROUTING FOR EMBEDDED APPLICATIONS SHARING A SINGLE NETWORK INTERFACE OVER MULTIPLE VIRTUAL NETWORKS - Techniques are provided for packet routing in a distributed network switch. The distributed network switch includes multiple switch modules operatively connected to one another, and each switch module includes multiple bridge elements and a management controller. In one embodiment, a shared interface routing (SIR) framework is provided that includes an analysis and bifurcation layer and at least one packet interface. A packet is received over a first logical network and via a physical port, the packet being destined for at least a first application executing on the management controller. The analysis and bifurcation layer analyzes the packet and sends the packet to the packet interface, which then routes the packet to the first application. | 08-15-2013 |
20130208728 | PACKET ROUTING FOR EMBEDDED APPLICATIONS SHARING A SINGLE NETWORK INTERFACE OVER MULTIPLE VIRTUAL NETWORKS - Techniques are provided for packet routing in a distributed network switch. The distributed network switch includes multiple switch modules operatively connected to one another, and each switch module includes multiple bridge elements and a management controller. In one embodiment, a shared interface routing (SIR) framework is provided that includes an analysis and bifurcation layer and at least one packet interface. A packet is received over a first logical network and via a physical port, the packet being destined for at least a first application executing on the management controller. The analysis and bifurcation layer analyzes the packet and sends the packet to the packet interface, which then routes the packet to the first application. | 08-15-2013 |
20130212308 | MEMORY MAPPED INPUT/OUTPUT BUS ADDRESS RANGE TRANSLATION - In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge. | 08-15-2013 |
20140075068 | CONCURRENT REPAIR OF PCIE SWITCH UNITS IN A TIGHTLY-COUPLED, MULTI-SWITCH, MULTI-ADAPTER, MULTI-HOST DISTRIBUTED SYSTEM - Techniques are disclosed to perform an operation to facilitate concurrent repair of PCIe switch units in processing environments such as a tightly coupled, multi-switch, multi-adapter, multi-host distributed system. The operation, for an identified switch unit to be repaired, reconfigures all switch unit hardware in the switch fabric by removing all upstream to downstream connections utilizing the identified switch unit. Connections to hosts via the upstream ports are also removed by the operation. Once the switch unit is powered back on, the operation reconfigures all switch unit hardware in the switch fabric by adding all upstream to downstream connections utilizing the identified switch unit. The operation further restores connections to hosts via the upstream ports. | 03-13-2014 |
20140075083 | CONCURRENT REPAIR OF THE PCIE SWITCH UNITS IN A TIGHTLY-COUPLED, MULTI-SWITCH, MULTI-ADAPTER, MULTI-HOST DISTRIBUTED SYSTEM - Techniques are disclosed to perform an operation to facilitate concurrent repair of PCIe switch units in processing environments such as a tightly coupled, multi-switch, multi-adapter, multi-host distributed system. The operation, for an identified switch unit to be repaired, reconfigures all switch unit hardware in the switch fabric by removing all upstream to downstream connections utilizing the identified switch unit. Connections to hosts via the upstream ports are also removed by the operation. Once the switch unit is powered back on, the operation reconfigures all switch unit hardware in the switch fabric by adding all upstream to downstream connections utilizing the identified switch unit. The operation further restores connections to hosts via the upstream ports. | 03-13-2014 |
20140086044 | FENCING OFF SWITCH DOMAINS - Techniques are disclosed to reduce crossover between traffic from switch elements of different switch domains in a distributed switch. Addition of a first switch element to the distributed switch is detected. The distributed switch includes multiple switch elements at least subsequent to the addition, and each switch element has a switch element identifier and a fabric identifier. The respective fabric identifiers of the first switch element and of a second switch element are retrieved. The second switch element is communicably connected to the first switch element via a link, and the link is configured to allow only command traffic to be transmitted via the link. Upon a determination that the fabric identifier of the first switch element does not match the fabric identifier of the second switch element, then no command is issued specifying to reconfigure the link to allow at least one additional traffic type, different from command traffic. | 03-27-2014 |
20140086051 | FENCING OFF SWITCH DOMAINS - Techniques are disclosed to reduce crossover between traffic from switch elements of different switch domains in a distributed switch. Addition of a first switch element to the distributed switch is detected. The distributed switch includes multiple switch elements at least subsequent to the addition, and each switch element has a switch element identifier and a fabric identifier. The respective fabric identifiers of the first switch element and of a second switch element are retrieved. The second switch element is communicably connected to the first switch element via a link, and the link is configured to allow only command traffic to be transmitted via the link. Upon a determination that the fabric identifier of the first switch element does not match the fabric identifier of the second switch element, then no command is issued specifying to reconfigure the link to allow at least one additional traffic type, different from command traffic. | 03-27-2014 |
20140173347 | FIRMWARE GENERATED REGISTER FILE FOR USE IN HARDWARE VALIDATION - When testing or validating a hardware system, a script file representing a portion of the firmware may be used to test the system instead of using the firmware code itself. For example, the script file may be plurality of register commands that perform the same initialization sequence as the firmware. Before connecting the hardware system to firmware drivers, the script file may be used to debug the initialization sequence. Instead of generating this script file manually, a firmware testing tool may be used. While executing the firmware, the tool may record the different register access commands performed during the initialization process. The script file is then generated programmatically using these recorded commands without requiring input from the system designer. The generated script file may then be tested on the hardware system to determine whether the command sequence in the script file forces the hardware system into the desired state. | 06-19-2014 |
20140173348 | FIRMWARE GENERATED REGISTER FILE FOR USE IN HARDWARE VALIDATION - When testing or validating a hardware system, a script file representing a portion of the firmware may be used to test the system instead of using the firmware code itself. For example, the script file may be plurality of register commands that perform the same initialization sequence as the firmware. Before connecting the hardware system to firmware drivers, the script file may be used to debug the initialization sequence. Instead of generating this script file manually, a firmware testing tool may be used. While executing the firmware, the tool may record the different register access commands performed during the initialization process. The script file is then generated programmatically using these recorded commands without requiring input from the system designer. The generated script file may then be tested on the hardware system to determine whether the command sequence in the script file forces the hardware system into the desired state. | 06-19-2014 |
20140201338 | CONFIGURATION OF NETWORK ENTITIES USING FIRMWARE - A method includes receiving firmware at a network entity and determining whether the network entity is to operate as a controlling Fiber Channel forwarder based on the firmware. | 07-17-2014 |