Patent application number | Description | Published |
20080270861 | NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD - A method of synchronous digital operation and scan based testing of an integrated circuit using a flip-flop. The flip-flop including a master latch having an input and a clock pin; a slave latch having an output, a first clock pin and a second clock pin, the slave latch connected to the to the master latch; a first AND gate having a first input, an inverted second input and an output, the output of the first AND gate connected to the first clock pin of the master latch; a second AND gate having a first input, an inverted second input and an output, the output of the second AND gate connected to the second input of the first AND gate and to the first clock pin of the slave latch. | 10-30-2008 |
20080270863 | METHODS OF SYNCHRONOUS DIGITAL OPERATION AND SCAN BASED TESTING OF AN INTEGRATED CIRCUIT USING NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD - A method of synchronous digital operation and scan based testing of an integrated circuit using a flip-flop. The method including: providing a flip-flop comprising: a master latch having an input and a clock pin; and a slave latch having an output, a first clock pin and a second clock pin; capturing data presented at said input of said master latch and transferring data stored in said master latch to said slave latch in response to a negative edge of a first clock signal on said clock pin of said master latch; launching data stored in said slave latch to said output of said slave latch in response to said negative edge of said first clock signal; and capturing data presented at said input of said master latch in response to a positive edge of a second clock signal on said clock pin of said master latch. | 10-30-2008 |
20080270953 | IC CHIP AT-FUNCTIONAL-SPEED TESTING WITH PROCESS COVERAGE EVALUATION - Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage. | 10-30-2008 |
20090055696 | MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST) - Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock. | 02-26-2009 |
20090094565 | METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT - A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications. | 04-09-2009 |
20090106608 | APPARATUS AND METHOD FOR SELECTIVELY IMPLEMENTING LAUNCH OFF SCAN CAPABILITY IN AT SPEED TESTING - An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain. | 04-23-2009 |
20090119629 | SYSTEM AND METHOD FOR GENERATING AT-SPEED STRUCTURAL TESTS TO IMPROVE PROCESS AND ENVIRONMENTAL PARAMETER SPACE COVERAGE - A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern. | 05-07-2009 |
20090150844 | CRITICAL PATH SELECTION FOR AT-SPEED TEST - A method of critical path selection provides a set of paths that initially contains no paths. A timing tool is used to identify potential critical paths of an integrated circuit design. Each potential critical path is evaluated and the potential critical path is added to the set of paths if logic devices within the potential critical path are shared by less than a predetermined number of critical paths within the set of paths. This evaluating and adding process is repeated for each of the potential critical paths until all of the potential critical paths have been evaluated. Then, the potential critical paths within the set of paths can be output. | 06-11-2009 |
20090199036 | LSSD compatibility for GSD unified global clock buffers - A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal. | 08-06-2009 |
20090265677 | INTEGRATED TEST WAVEFORM GENERATOR (TWG) AND CUSTOMER WAVEFORM GENERATOR (CWG), DESIGN STRUCTURE AND METHOD - Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both an external waveform generator and an internal waveform generator. The external waveform generator can generate and supply to the deskewer circuit a pair of waveform signals for functional operations. The internal waveform generator can be uniquely configured with control logic and counter logic for generating and supplying a pair of waveform signals to the deskewer circuit for any one of built-in self-test (BIST) operations, macro-test operations, other test operations or functional operations. The deskewer circuit can selectively gate an input clock signal with the waveform signals from either the external or internal waveform generator in order to generate the required output clock signal. | 10-22-2009 |
20090319818 | METHOD AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE - A method is provided for operating an interface between a first unit and a second unit supplying its data. The method includes switching control between LSSD_B and LSSD_C clocks and system clock (CLK) to provide a test mode of operation and a functional mode of operation to optimize setup and hold times depending on conditions under which the unit is operating. In the test mode, data is launched by the LSSD_C clock. In the functional mode, the data is launched by the system clock (CLK) to RAM. A method is also provided to determine which memory inputs should use a circuit that provides adequate setup and hold margins. | 12-24-2009 |
20090319841 | STRUCTURE AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes an input register coupled to a data processing unit input and a test operation mode and functional operation mode. In the test mode operation, the register operates in a clocked mode such that, during the test operation mode, the register propagates data to the data processing unit in response to a clock signal. In the functional operation mode, the register operates in a data flush mode such that the register propagates data to the data processing unit in response to the data. The functional mode is enabled by a flush enable signal and the test mode is enabled by an opposite state of the flush enable signal. | 12-24-2009 |
20120112341 | METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT - A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications. | 05-10-2012 |
20120115256 | METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT - A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications. | 05-10-2012 |
20120124538 | METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT - A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications. | 05-17-2012 |
20120179944 | DENSE REGISTER ARRAY FOR ENABLING SCAN OUT OBSERVATION OF BOTH L1 AND L2 LATCHES - A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data. | 07-12-2012 |
20120221910 | MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST) - Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock. | 08-30-2012 |
20130125073 | TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TESTING INTEGRATED CIRCUIT CHIPS - A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths | 05-16-2013 |
20130125076 | DISPOSITION OF INTEGRATED CIRCUITS USING PERFORMANCE SORT RING OSCILLATOR AND PERFORMANCE PATH TESTING - A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test. | 05-16-2013 |