Patent application number | Description | Published |
20080284474 | Techniques for integrated circuit clock management - A clock generator ( | 11-20-2008 |
20080284476 | Techniques for integrated circuit clock management using pulse skipping - A processor ( | 11-20-2008 |
20080285696 | Techniques for integrated circuit clock management using multiple clock generators - A clock generator system ( | 11-20-2008 |
20080288804 | Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test - An integrated circuit ( | 11-20-2008 |
20090108903 | LEVEL SHIFTER DEVICE - A first transistor of a level shifter provides conductivity between a reference voltage and a node of the level shifter to hold a state of the level shifter output. When an input signal of the level shifter switches, additional transistors assist in reducing the conductivity of the first transistor. This enhances the ability of the level shifter to change the state of the output in response to the change in the input signal, thereby improving the writeability of the level shifter. | 04-30-2009 |
20090140819 | POWER MONITORING DEVICE AND METHODS THEREOF - To determine performance degradation at functional module in a normal power state due to a power control device, voltages are applied to oscillators at a power diagnostic module. A first voltage is a supply voltage for the data processing device, and a second voltage is a supply voltage applied at a functional module of the data processing device. Counters are adjusted based on the oscillators to determine the oscillators' respective frequencies. In addition, the power diagnostic module can include a timer to measure the length of time that the functional module is in a low-power state, and an analog to digital converter to measure the voltage applied to the functional module during transitions to and from the low-power state. | 06-04-2009 |
20100007396 | COMPOUND LOGIC FLIP-FLOP HAVING A PLURALITY OF INPUT STAGES - A compound logic flip-flop. The flip-flop includes a plurality of input stages, wherein each of the input stages is coupled to receive at least one input signal and a clock signal. Each of the plurality of input (i.e. ‘master’) stages is configured to perform a corresponding input logic function during a first phase of a clock cycle and to store a result of the corresponding input logic function. The flip-flop further includes an output (i.e. ‘slave’) stage coupled to receive the clock signal and the results of the input logic functions from each of the plurality of input stages. The output stage is configured, during a second phase of the clock cycle, to logically combine the results of the input logic functions by performing an output logic function and provide an output signal based on a result of the output logic function. | 01-14-2010 |
20120119816 | VARIABLE-WIDTH POWER GATING MODULE - A semiconductor device includes a primary voltage rail, a secondary voltage rail, a plurality of transistors coupled between the primary and secondary voltage rails, and control logic operable to enable a first subset of the plurality of transistors to couple the primary voltage rail to the secondary voltage rail. During a steady state condition, the first subset comprises less than all of the plurality of transistors. | 05-17-2012 |
20130009693 | PIPELINE POWER GATING FOR GATES WITH MULTIPLE DESTINATIONS - A first and second plurality of gates are coupled respectively between first and second source storage elements and first and second destination storage elements. The first and second plurality of gates are slept to reduce leakage current in the plurality of gates under certain conditions by turning off respective one or more transistors between the first and second plurality of gates and power supplies. A third plurality of gates are maintained in a reduced leakage current state (sleep state) or regular state (wake state) based on conditions associated with the source and destination elements for the first and second plurality of gates. | 01-10-2013 |
20130009697 | PIPELINE POWER GATING - Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements. | 01-10-2013 |