Patent application number | Description | Published |
20150255142 | Compact System with Memory and PMU Integration - One or more integrated circuits including at least one integrated circuit that is fabricated in a DRAM fabrication process. Capacitors in the DRAM-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip PMUs. Embedded DRAM memories can be used instead of SRAM memories, with increased density and reduced leakage. More compact systems can be implemented using the integrated circuits. | 09-10-2015 |
20150270258 | Optimized ESD Clamp Circuitry - ESD protection circuitry is disclosed. In one embodiment, an integrated circuit includes first and second sensor circuits. The first sensor circuit has a first resistive-capacitive (RC) time constant, while the second sensor circuit has a second RC time constant. The RC time constant of the first sensor circuit is at least one order of magnitude greater than that of the second sensor circuit. A first clamp transistor is coupled to and configured to be activated by the first sensor circuit responsive to the latter detecting an ESD event. A second clamp transistor is coupled to and configured to be activated by the second sensor circuit responsive to the latter detecting the ESD event. | 09-24-2015 |
20150380397 | ESD Protection for Advanced CMOS Processes - Various embodiments of ESD protection circuits and methods for operating the same are disclosed. In one embodiment, one or more driver circuits are protected by a first ESD protection circuit configured to activate and discharge current responsive to an ESD event. The driver circuit may include a pull-up transistor and a pull-down transistor each coupled to drive an output node. A second ESD protection circuit may be associated with and dedicated to the pull-up transistor in the driver circuit. | 12-31-2015 |
20160034025 | Physical Layer for Peripheral Interconnect with Reduced Power and Area - An integrated circuit (IC) implements an industry standard-defined peripheral interconnect to connect to another integrated circuit or component in a system. The industry standard specification includes a software interface that is well-defined and implemented by various software in the system, and thus is desirable to retain. However, the physical interconnect in the systems employing the integrated circuit may be short, and thus the elaborate physical layer definition may consume more integrated circuit area and power than is otherwise desirable in the IC. The IC may implement a simpler and more power-efficient physical layer, reducing both power consumption and semiconductor substrate area consumption, in some embodiments. | 02-04-2016 |