Craig Warner
Craig Warner, Aspen Court, TX US
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20090037671 | HARDWARE DEVICE DATA BUFFER - One embodiment includes a system comprising a processor configured to read and write data packets via a data bus to and from at least one additional hardware device. The system also comprises a data buffer configured to store a plurality of consecutive related flits associated with at least one of the data packets in one of a plurality of addressable locations of the data buffer. The system further comprises a pointer memory configured to store a respective pointer associated with each of the plurality of addressable locations of the data buffer. | 02-05-2009 |
20100082912 | SYSTEMS AND METHODS FOR RESOURCE ACCESS - Systems and methods are provided to manage access to computing resources. More specifically, certain embodiments are described in which a resource or resource consumer can engage access controls or request that access controls be engaged if the age of a request exceeds one or more thresholds. For example, a requester may, after the age of a request meets or exceeds a threshold, indicate to a destination that a control should be engaged. | 04-01-2010 |
Craig Warner, North Ridgeville, OH US
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20090031778 | Multi-application crimping or pressing tool - A manual or powered crimping tool, and corresponding jaw set, are described that include a combination of provisions for crimping tangential type crimping elements and one or more circumferential type crimping elements. Various versions of the tool and jaw set are provided including tools and jaw sets that include provisions for using a selectively replaceable insert that significantly increases the range of applications of the tool or jaw set. Tool versions are also provided having insert receiving surfaces, such as when used with inserts, that also serve as crimping surfaces. | 02-05-2009 |
20100005691 | IDENTIFICATION ATTACHMENTS FOR COMPRESSION TOOLS - An identification attachment is provided for a compression tool of the character having a pair of jawarms pivotally mounted between a pair of side plates by pivot pins having outer ends including pin retainers for maintaining the jawarms and side plates in assembled relationship. The jawarms have opposite sides, inner and outer edges and front and rear ends, respectively forwardly and rearwardly of the side plates, and the identification attachment is removably mountable on the tool independent of any mounting openings for the attachment extending through the jawarms. The attachment may, for example, interengage with opposite sides of a jawarm or be captured on the tool by the pin retainers or the side plates. | 01-14-2010 |
Craig Warner, Addison, TX US
Patent application number | Description | Published |
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20080256306 | NON-INCLUSIVE CACHE SYSTEMS AND METHODS - Non-inclusive cache systems and methods are provided. In one embodiment a non-inclusive cache system is provided comprising a non-inclusive cache and a cache agent that receives a request for access to the non-inclusive cache and denies the request for access to the non-inclusive cache if the non-inclusive cache system exceeds a predetermined level of activity. | 10-16-2008 |
20090094418 | SYSTEM AND METHOD FOR ACHIEVING CACHE COHERENCY WITHIN MULTIPROCESSOR COMPUTER SYSTEM - An embodiment of a multiprocessor computer system comprises main memory, a remote processor capable of accessing the main memory, a remote cache device operative to store accesses by said remote processor to said main memory, and a filter tag cache device associated with the main memory. The filter cache device is operative to store information relating to remote ownership of data in the main memory including ownership by the remote processor. The filter cache device is operative to selectively invalidate filter tag cache entries when space is required in the filter tag cache device for new cache entries. The remote cache device is responsive to events indicating that a cache entry has low value to the remote processor to send a hint to the filter tag cache device. The filter tag cache device is responsive to a hint in selecting a filter tag cache entry to invalidate. | 04-09-2009 |
Craig Warner, Richardson, TX US
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20080270708 | System and Method for Achieving Cache Coherency Within Multiprocessor Computer System - A system and method are disclosed for achieving cache coherency in a multiprocessor computer system having a plurality of sockets with processing devices and memory controllers and a plurality of memory blocks. In at least some embodiments, the system includes a plurality of node controllers capable of being respectively coupled to the respective sockets of the multiprocessor computer, a plurality of caching devices respectively coupled to the respective node controllers, and a fabric coupling the respective node controllers, by which cache line request signals can be communicated between the respective node controllers. Cache coherency is achieved notwithstanding the cache line request signals communicated between the respective node controllers due at least in part to communications between the node controllers and the respective caching devices to which the node controllers are coupled. In at least some embodiments, the caching devices track remote cache line ownership for processor and/or input/output hub caches. | 10-30-2008 |
20080270743 | System and Method for Achieving Enhanced Memory Access Capabilities - A computer system, related components such as a processor agent, and related method are disclosed. In at least one embodiment, the computer system includes a first core, at least one memory device including a first memory segment, and a first memory controller coupled to the first memory segment. Further, the computer system includes a fabric and at least one processor agent coupled at least indirectly to the first core and the first memory segment, and also coupled to the fabric. A first memory request of the first core in relation to a first memory location within the first memory segment proceeds to the first memory controller by way of the at least one processor agent and the fabric. | 10-30-2008 |
20110179423 | MANAGING LATENCIES IN A MULTIPROCESSOR INTERCONNECT - In a computing system having a plurality of transaction source nodes issuing transactions into a switching fabric, an underserviced node notifies source nodes in the system that it needs additional system bandwidth to timely complete an ongoing transaction. The notified nodes continue to process already started transactions to completion, but stop the introduction of new traffic into the fabric until such time as the underserviced node indicates that it has progressed to a preselected point. | 07-21-2011 |
Craig Warner, Palo Alto, CA US
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20130317905 | METHODS AND SYSTEMS FOR IDENTIFYING NEW COMPUTERS AND PROVIDING MATCHING SERVICES - A method of providing services to computing devices includes establishing a connection over the Internet with a computing device; receiving data from the computing device during the connection; extracting a signal from the data received from the computing device; estimating a relative age of the computing device based on the extracted signal; selecting a service from a plurality of services based on the estimated relative age of the computing device; and providing the selected service to the computing device. | 11-28-2013 |
Craig Warner, Coppell, TX US
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20140250274 | MAPPING PERSISTENT STORAGE - A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors, in a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent. | 09-04-2014 |
20150052308 | PRIORITIZED CONFLICT HANDLING IN A SYSTEM - A controller has a cache to store data associated with an address that is subject to conflict resolution. A conflict resolution queue stores information relating to plural transactions, and logic reprioritizes the plural transactions in the conflict resolution queue to change a priority of a first type of transaction with respect to a priority of second type of transaction. | 02-19-2015 |
Craig Warner, Irving, TX US
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20150052293 | HIDDEN CORE TO FETCH DATA - A computing device includes a home node controller to couple a home processor socket to the computing device. The home processor socket includes a home core hidden from the computing device and the home core fetches data to a home cache of the home processor socket. The computing device includes a source processor socket including a source core to request for data and the home node controller forwards requested data from the home cache to the source core if the requested data is included on the home cache. | 02-19-2015 |
20150081982 | SHIELDING A MEMORY DEVICE - A method of shielding a memory device ( | 03-19-2015 |