Patent application number | Description | Published |
20120026802 | MANAGED HYBRID MEMORY WITH ADAPTIVE POWER SUPPLY - Subject matter disclosed herein relates to a memory device, and more particularly to a managed hybrid memory that includes a power supply. | 02-02-2012 |
20120137093 | RELIABLE WRITE FOR NON-VOLATILE MEMORY - Example embodiments described herein may relate to performing reliable right commands for non-volatile memory devices. | 05-31-2012 |
20120226880 | APPARATUS, ELECTRONIC DEVICES AND METHODS ASSOCIATED WITH AN OPERATIVE TRANSITION FROM A FIRST INTERFACE TO A SECOND INTERFACE - Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes. | 09-06-2012 |
20130019058 | MULTI-PARTITIONING OF MEMORIES - Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described. | 01-17-2013 |
20130219105 | METHOD, DEVICE AND SYSTEM FOR CACHING FOR NON-VOLATILE MEMORY DEVICE - Example embodiments described herein may relate to memory devices, and may relate more particularly to caching for non-volatile memory devices. | 08-22-2013 |
20130219146 | METHOD, DEVICE AND SYSTEM FOR A CONFIGURABLE ADDRESS SPACE FOR NON-VOLATILE MEMORY - Example embodiments described herein may relate to memory devices, and may relate more particularly to configurable address space for non-volatile memory devices. | 08-22-2013 |
20150032927 | APPARATUS, ELECTRONIC DEVICES AND METHODS ASSOCIATED WITH AN OPERATIVE TRANSITION FROM A FIRST INTERFACE TO A SECOND INTERFACE - Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes. | 01-29-2015 |
Patent application number | Description | Published |
20080212369 | METHOD OF MANAGING A MEMORY DEVICE EMPLOYING THREE-LEVEL CELLS - A method of managing a multi-level memory device having singularly addressable three-level cells includes storing strings of three bits by coding them in corresponding ternary strings according to a coding scheme and writing each of the ternary strings in a respective pair of three-level cells. Strings of three bits are read by reading respective ternary strings written in respective pairs of three-level cells and decoding each read ternary string in a corresponding string of three bits according to the coding scheme. A pair of adjacent bits, belonging to at least one of a same initial string and two initial adjacent strings, are programmed by identifying pairs of three-level cells to be programmed that encode the strings of three bits and programming each pair of three-level cells. | 09-04-2008 |
20100202194 | DYNAMICALLY ALLOCABLE REGIONS IN NON-VOLATILE MEMORIES - An embodiment of a non-volatile memory device is proposed. Said memory device comprises a matrix of memory cells; each memory cell is individually programmable to at least a first logic level and individually erasable to a second logic level. The memory device further comprises partition means for logically subdividing the matrix into a plurality of subspaces; each subspace comprises at least one respective memory cell. The memory device further comprises selection means for selecting a subspace, operative means for performing an operation on all the memory cells of the selected subspace, and means for dynamically modifying the number of subspaces and/or the number of memory cells included in each subspace. | 08-12-2010 |
20120191924 | PREPARATION OF MEMORY DEVICE FOR ACCESS USING MEMORY ACCESS TYPE INDICATOR SIGNAL - Subject matter disclosed herein relates to memory devices or accessing memory devices, and more particularly, but by way of example and not limitation, to preparation of a memory device to perform a memory access operation based at least partly on at least one indicator signal that indicates a memory access type. | 07-26-2012 |
20140223087 | MULTI-PARTITIONING OF MEMORIES - Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described. | 08-07-2014 |
Patent application number | Description | Published |
20100153820 | MEMORY WITH GUARD VALUE DEPENDENT ERROR CORRECTION - Embodiments of the present disclosure provide methods, systems, and apparatuses related to calculating an error correction code for a program page dependent on guard values that correspond to words of the program page. Other embodiments may be described and claimed. | 06-17-2010 |
20100293317 | PCM MEMORIES FOR STORAGE BUS INTERFACES - A memory controller for a phase change memory (PCM) that can be used on a storage bus interface is described. In one example, the memory controller includes an external bus interface coupled to an external bus to communicate read and write instructions with an external device, a memory array interface coupled to a memory array to perform reads and writes on a memory array, and an overwrite module to write a desired value to a desired address of the memory array. | 11-18-2010 |
20110302353 | NON-VOLATILE MEMORY WITH EXTENDED OPERATING TEMPERATURE RANGE - A method and apparatus are described for measuring a temperature within a non-volatile memory and refreshing at least a portion of the non-volatile memory when the temperature exceeds a threshold temperature for an amount of time. | 12-08-2011 |
20120033519 | TEMPERATURE ALERT AND LOW RATE REFRESH FOR A NON-VOLATILE MEMORY - A method and apparatus are described for measuring a temperature within a non-volatile memory, storing, in a register within the non-volatile memory, a temperature alert comprising one or more bits indicating the non-volatile memory has exceeded a threshold temperature for a period of time, determining, by a host, that the temperature alert is active, and in response to the determination that the temperature alert is active, refreshing at least a portion of the non-volatile memory. | 02-09-2012 |
20120124313 | MULTI-CHANNEL MEMORY WITH EMBEDDED CHANNEL SELECTION - Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same. | 05-17-2012 |
20120163082 | MEMORY WITH SUB-BLOCKS - The apparatuses and methods described herein may comprise a memory array formed on a semiconductor substrate and including a plurality of cells associated with a plurality of word lines. The memory array may comprise a plurality of sub-blocks including a first sub-block and a second sub-block. Each sub-block may comprise a memory cell portion of the plurality of memory cells associated with a corresponding word line portion of the plurality of word lines. The memory cell portions in the first and second sub-blocks may be independently addressable with respect to each other such that a second operation can be performed on at least one memory cell of the memory cell portion of the second sub-block responsive to suspending a first operation directed to at least one memory cell of the memory cell portion of the first sub-block. | 06-28-2012 |
20120290812 | CONFIGURABLE PARTITIONS FOR NON-VOLATILE MEMORY - Example embodiments for configuring a non-volatile memory device may comprise configuring M physical partitions of the non-volatile memory into two or more banks, wherein the two or more banks respectively comprise one or more of the M physical partitions, and wherein at least a first of the M physical partitions comprises a first size and wherein at least a second of the M physical partitions comprises a second size. | 11-15-2012 |
20120317347 | CONTROL AND OPERATION OF NON-VOLATILE MEMORY - Various embodiments comprise apparatuses and methods including a memory controller to control a non-volatile memory array. The memory controller includes a memory array interface coupled to the non-volatile memory array to perform reads and writes on the non-volatile memory array. An overwrite module is configured to write a desired bit value to a specific memory cell within the non-volatile memory array, after receiving the desired bit value and a logical address, regardless of an original value of the memory cell Additional apparatuses and methods are described. | 12-13-2012 |
20120320701 | MULTI-CHANNEL MEMORY AND POWER SUPPLY-DRIVEN CHANNEL SELECTION - Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same. | 12-20-2012 |
20140112071 | MULTI-CHANNEL MEMORY AND POWER SUPPLY-DRIVEN CHANNEL SELECTION - Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same. | 04-24-2014 |
20140149823 | MEMORY WITH GUARD VALUE DEPENDENT ERROR CORRECTION - Embodiments of the present disclosure provide methods, systems, and apparatuses related to calculating an error correction code for a program page dependent on guard values that correspond to words of the program page. Other embodiments may be described and claimed. | 05-29-2014 |
20150067254 | Multi-Interface Memory With Access Control - Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same. | 03-05-2015 |