Patent application number | Description | Published |
20100182833 | MEMORY AND BOUNDARY SEARCHING METHOD THEREOF - A memory and a boundary searching method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the boundary of the threshold voltage distribution could be determined precisely. | 07-22-2010 |
20100226180 | MEMORY ARRAY AND METHOD OF OPERATING A MEMORY - A memory array is described, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source and the drain of a memory cell to be read do not vary with the memory cell to be read. | 09-09-2010 |
20110016370 | MEMORY APPARATUS AND OPERATION METHOD THEREOF - A memory apparatus and an operation method thereof are provided. The memory apparatus includes a plurality of multi-level cells and a controller. The controller encodes input data according to a target encoding code to generate a plurality of encoded subsets, and stores the encoded subsets into the multi-level cells. Thereafter, the controller could read data from the multi-level cells, perform an error correction procedure on the read data to correct and recover the read data as recovered data, and decode the recovered data according to the target encoding code. Consequently, sensing windows between threshold voltage distributions of the multi-level cells are expanded. | 01-20-2011 |
20110157986 | MEMORY AND OPERATING METHOD THEREOF - A memory and an operating method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the boundary of the threshold voltage distribution could be determined precisely. | 06-30-2011 |
20110267881 | MEMORY ARRAY - A memory array is shown, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source and the drain of a memory cell to be read do not vary with the memory cell to be read. | 11-03-2011 |
20160049178 | METHOD AND APPARATUS FOR ADJUSTING DRAIN BIAS OF A MEMORY CELL WITH ADDRESSED AND NEIGHBOR BITS - The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part; the different parts can be in different, neighboring memory cells. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window. | 02-18-2016 |
Patent application number | Description | Published |
20130100758 | LOCAL WORD LINE DRIVER - A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage reference signal, and an input signal. The word line driver has an output coupled to a word line. The control circuitry is configured to deselect the word line by applying the input signal to the input of the word line driver. For example, in a program operation the word line is deselected to indicate that the word line is not programmed, and another word line is selected to be programmed. During an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver. | 04-25-2013 |
20130128670 | MEMORY ACCESS METHOD AND FLASH MEMORY USING THE SAME - A memory access method is applied in a memory controller for accessing an NAND memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes the following steps. A stream bias signal and a selected word line signal are respectively provided on a selected stream and on a selected cell of the selected stream, and the rest of memory cells are turned on as pass transistors, in the setup phase. A discharge path is provided to eliminate coupling charge presented on unselected streams, in the setup phase. Then, the string select signal is enabled to have the selected stream connected to a sense unit via a metal bit line and according read the selected cell in a voltage sensing scheme, in a read phase, which does not overlap with the setup phase. | 05-23-2013 |
20130148445 | LOCAL WORD LINE DRIVER - A memory circuit with a word line driver and control circuitry is disclosed. The plurality of word line drivers are coupled to a plurality of word lines. Word line drivers include a CMOS inverter, which can have an input and an output, and a p-type transistor and an n-type transistor. The output of the CMOS inverter is coupled to one of the plurality of word lines. The control circuitry has multiple modes, including at least a first mode to discharge a particular word line of the plurality of word lines via a first discharge path such as at least a first transistor type of the CMOS inverter; and a second mode to discharge the particular word line of the plurality of word lines via a second discharge path such as at least the a second transistor type of the CMOS inverter. | 06-13-2013 |
20130208552 | Method and Apparatus for Adjusting Drain Bias of A Memory Cell With Addressed and Neighbor Bits - The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window. | 08-15-2013 |
20130215687 | Method and Apparatus for Dynamic Sensing Window in Memory - A memory array is characterized by a threshold definition, which includes threshold voltage ranges representing data values stored by a part of the memory array, and a set of sense windows separating the threshold voltage ranges. The threshold definition is varied, responsive to at least one of program operations and erase operations. Such operations change a distribution of the data values stored in the memory group. | 08-22-2013 |
20130286744 | Bit Line Bias Circuit With Varying Voltage Drop - A bit line bias circuit of a memory architecture includes a varying voltage drop. In some embodiments, the voltage drop can depend on the threshold voltage of the memory cell selected to be read, or on the sense current flowing through the memory cell selected to be read. | 10-31-2013 |
20130314997 | Memory Access Method and Flash Memory Using the Same - A memory access method is applied in a memory controller for accessing a memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes: enabling the string select signal and disabling the string select signal before a read phase. | 11-28-2013 |
20140146611 | MEMORY DEVICE AND METHOD FOR PROGRAMMING MEMORY CELL OF MEMORY DEVICE - A method for programming a memory cell of a memory device includes the following steps. A plurality of cycle number ranges are set up. A specific one of the plurality of cycle number ranges, in which the memory cell having a drain terminal passes a program-verification, is determined. A bias voltage is applied to the drain terminal for programming the memory cell, wherein the bias voltage varies with the specific cycle number range. | 05-29-2014 |
20150085588 | METHOD AND APPARATUS FOR ADJUSTING DRAIN BIAS OF A MEMORY CELL WITH ADDRESSED AND NEIGHBOR BITS - The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window. | 03-26-2015 |
20150098279 | SENSING AMPLIFIER AND SENSING METHOD THEREOF - A sensing amplifier comprising a clamp circuit is provided. The clamp circuit is coupled between a first node and a second node. The clamp circuit comprises a first P-type transistor having a first terminal, a second terminal and a control terminal receiving a first bias signal, the first terminal and the second terminal of the first P-type transistor are coupled to the first node and the second node, respectively, and a sensing current from the memory cell flows into the second node via the first node during a sensing time period. | 04-09-2015 |
20150123708 | INTEGRATED CIRCUIT FOR MEMORY AND OPERATING METHOD THEREOF - An integrated circuit of a memory is provided. The integrated circuit comprises a first data driving circuit and a transmitting transistor. The first data driving circuit outputs a first data voltage to a first node. The transmitting transistor is coupled between the first node and a second node. When the transmitting transistor receives a bias voltage and the voltage level of the first node is a first voltage level, the transmitting transistor makes the voltage level of the second node to be set as a third voltage level, third voltage level is close to or substantially equal to the first voltage level. When the transmitting transistor receives the bias voltage and the voltage level of the first node is the second voltage level, the voltage level of the second node is independently of the voltage level of the first node. | 05-07-2015 |
20150212875 | DYNAMIC DATA DENSITY ECC - A method for operating a memory includes receiving an input data set, saving a first level error correcting code ECC for the data in the input data set, saving second level ECCs for a plurality of second level groups of the data in the data set, storing the data set in the memory, and testing the data set to determine whether to use the first level ECC or the second level ECCs. The method includes, if the first level ECC is used, storing a flag enabling use of the first level ECC, else if the second level ECCs are used, storing a flag enabling use of the second level ECCs. The method includes storing the second level ECCs in a replacement ECC memory, and storing a pointer indicating locations of the second level ECCs in the replacement ECC memory. | 07-30-2015 |
20160042794 | LEVEL SHIFTER AND DECODER FOR MEMORY - A level shifter receiving an input with a relatively narrow voltage range and provides an output with a relatively wide voltage range. The level shifter including a transistor with a turn-on voltage. Control circuitry applies a bias to the level shifter such that the transistor does not receive the turn-on voltage. | 02-11-2016 |
20160099069 | PROGRAM VERIFY WITH MULTIPLE SENSING - A sense circuit is coupled to a bit line of a memory array. Control circuitry coupled to the sense circuit controls a program operation for a memory cell. After a program phase in which the memory cell in the memory array is programmed, in a program verify phase the control circuitry causes the sense circuit to sense data stored on the memory cell multiple times during the program verify phase. The multiple times include a first time sensing data from the memory cell and a second time sensing data from the memory cell. | 04-07-2016 |
20160103763 | MEMORY PAGE BUFFER - One aspect of the technology is a memory device, which comprises a plurality of page buffers and control circuitry. Different page buffer circuits in the plurality of page buffer circuits are coupled to different bit lines in a plurality of bit lines in a memory array. The control circuitry is responsive to a program command to program multiple cells in the memory array, by setting, via the plurality of page buffer circuits, different target voltages at a same time for the different bit lines coupled to the multiple cells. | 04-14-2016 |
20160125922 | THRESHOLD VOLTAGE GROUPING OF MEMORY CELLS IN SAME THRESHOLD VOLTAGE RANGE - A memory cell undergoing programming is determined as belonging to a particular one of a plurality of second threshold voltage ranges that divide a present threshold voltage range of the particular memory cell. Programming pulses are applied to program the particular memory cell to within the target threshold voltage range. At least one of a program voltage and a total duration of the programming pulses applied to the particular memory cell is varied, depending on the particular second threshold voltage range of the memory cell. | 05-05-2016 |
Patent application number | Description | Published |
20090128115 | VOLTAGE REGULATOR AND CONTROLLING METHOD THEREOF - A controlling method of a voltage regulator is provided. The voltage regulator at least includes a differential circuit and a pump high-voltage circuit which has a bias path, an output transistor and an output terminal. The controlling method includes steps of: providing at least a pre-charge path to the pump high-voltage circuit, closing the bias path and charging the output terminal with the pre-charge path when the output terminal is transient, detecting an output level of the output terminal, and closing the pre-charge path and open the bias path to bias the output transistor when the output level reaches a predetermined value. | 05-21-2009 |
20130155777 | CURRENT SENSING TYPE SENSE AMPLIFIER AND METHOD THEREOF - The configurations of sense amplifier and methods thereof are provided. The proposed sense amplifier includes a switch circuit having a main control switch, a sensing switch and a holding switch, wherein the three switches have a first bias, a second bias and a third bias respectively, and an auxiliary control switch electrically connected to the holding switch to control an operation of the holding switch. | 06-20-2013 |
20130208544 | FLASH MEMORY WITH READ TRACKING CLOCK AND METHOD THEREOF - The configurations of a flash memory having a read tracking clock and method thereof are provided. The proposed flash memory includes a first and a second storage capacitors, a first current source providing a first current flowing through the first storage capacitor, a second current source providing a second current flowing through the second storage capacitor, and a comparator electrically connected to the first and the second current sources, and sending out a signal indicating a developing time being accomplished when the second current is larger than the first current. | 08-15-2013 |
20140232461 | SENSE AMPLIFIER SYSTEM AND SENSING METHOD THEREOF - A sense amplifier system and sensing method thereof are provided. The proposed sense amplifier system includes plural sense amplifiers, each of which includes a first switch having a first terminal, a second terminal, and a bulk terminal electrically connected to the first terminal, a second switch having a first terminal electrically connected to the second terminal of the first switch, a second terminal, and a bulk terminal, a third switch having a first terminal electrically connected to the first terminal of the second switch, a second terminal, and a bulk terminal electrically connected to the bulk terminal of the second switch, and a fourth switch having a first terminal electrically connected to the bulk terminal of the first switch and a second terminal electrically connected to the bulk terminal of the third switch. | 08-21-2014 |
Patent application number | Description | Published |
20110171600 | Bio-Implant Having a Screw Body with Nanoporous Spiral Groove and the Method of Making the Same - A bio-implant having a screw body selectively formed with nanoporous channels structure in a spiral groove and the method of making the same are disclosed. Nanoporous channels structure formed into the spiral groove of the bio-implant is carried out by the heat treatment in vacuum firstly and anodic treatment secondly. Thereafter, bioactive material is filled into the nanoporous and deposited on the implant surface by an electro-deposition process so as to increase the bioactivity and biocompatibility of the bio-implant. | 07-14-2011 |
20110195378 | Composite Bio-Ceramic Dental Implant and Fabricating Method Thereof - A composite bio-ceramic dental implant and fabricating method thereof are disclosed. The composite bio-ceramic is sintered at a temperature between 1000 and 1800° C. using the nearly inert bio-ceramic powder and the active bio-ceramic powder or the completely resorbable bio-ceramic powder. The bioactive bio-ceramic material is dispersed in the inert bio-ceramic material. Therefore, the composite bio-ceramic has enough mechanical strength and good bioactivity for dental implant. | 08-11-2011 |
20120012775 | ELECTROLYTE ADDITIVE OF DYE-SENSITIZED SOLAR CELL AND METHOD OF MAKING THE SAME - An electrolyte additive is selected from N-alkyl benzimidazole derivatives and is applicable to dye-sensitized solar cells. Accordingly, the electrolyte additive can be added to electrolyte at low concentration, and loss of function due to crystallization after long-term use can be prevented; in addition, short circuit photocurrent density and solar energy-to-electricity conversion efficiency of solar cells incorporating the electrolyte additive can be increased. | 01-19-2012 |
20120070566 | Dispersing Agent of MWCNTs and the Method for Preparation and Application of Homogeneous MWCNTs Dispersion - Dispersing agent of MWCNTs and the method for preparation of homogeneous MWCNTs dispersion are disclosed. Acid yellow 9(4-amino-1-1′-azobenzene-3,4′-disulfonic acid, AY) is a good agent for multi-walled carbon nanotubes (MWCNTs). MWCNTs dispersed in AY solution was remained stable about three months and even remained stable after centrifugation at 10000 rpm for 30 min. Using MWCNTs/AY dispersion, thin-films were prepared on indium tin oxide coated glass electrode and glassy carbon electrode. Further, dried firms of MWCNTs/AY were subjected to electropolymerization in 0.1 M H | 03-22-2012 |
20130150227 | Composite Bio-Ceramic Dental Implant and Fabricating Method Thereof - A composite bio-ceramic dental implant and fabricating method thereof are disclosed. The composite bio-ceramic is sintered at a temperature between 1000 and 1800° C. using the nearly inert bio-ceramic powder and the active bio-ceramic powder or the completely resorbable bio-ceramic powder. The bioactive bio-ceramic material is dispersed in the inert bio-ceramic material. Therefore, the composite bio-ceramic has enough mechanical strength and good bioactivity for dental implant. | 06-13-2013 |
20140144880 | Method of Surface Treatment for Zirconia Dental Implants - A method of surface treatment for zirconium oxide implants and the etching formula for the same are disclosed. The processes are carried out at room temperature. The average surface roughness Ra and the standard deviation of the implant are measured showing significant improvement while comparing with the un-treated sample and the hydrofluoric acid treated samples. The average contact angle is provided showing an almost hydrophilic surface after etched by the formula according to the present invention. | 05-29-2014 |