Patent application number | Description | Published |
20110039922 | 18beta-GLYCYRRHETINIC ACID DERIVATIVES AND SYNTHETIC METHOD THEREOF - The present invention provides a chemical compound having the structure being one selected from a group consisting of | 02-17-2011 |
20110190388 | URSOLIC ACID DERIVATIVE AND PHARMACEUTICAL COMPOSITION THEREOF - Several ursolic acid derivatives and pharmaceutical compositions thereof are provided. The ursolic acid derivatives and the pharmaceutical compositions thereof have at least one of an anticancer and an anti-inflammatory effects. A method for increasing a reactive oxygen species in a cell is also provided. The method comprises a step of providing the cell with a pharmaceutical composition including an ursolic acid derivative. | 08-04-2011 |
20110306775 | SYNTHESIS AND BIOLOGICAL EVALUATION OF 2',5'-DIMETHOXYCHALCONE DERIVATIVES AS MICROTUBULE-TARGETED ANTICANCER AGENTS - Disclosed are a serious of 2′,5′-dimethoxychalcone derivatives for treating cancer, wherein 2,5-dimethoxyacetophenone and methyl 4-formylbenzoate are condensed to form 4-carboxyl-2′,5′-dimethoxychalcone (compound 1), which is further reacted with alkyl halides or amines to synthesize the chalcone derivatives of compounds 2-17. In addition, 2,5-dimethoxyacetophenone is reacted with 5-formyl-2-thiophenecarboxylic acid to form compound 18 (3-(3-thiophene)carboxyl-1-(2,5-dimethoxyphenyl)prop-2-en-1-one). The synthesized 2′,5′-dimethoxychalcone derivatives can be acted as microtubule-targeted tubulin-polymerizing agents. | 12-15-2011 |
20130072694 | 18 -GLYCYRRHETINIC ACID DERIVATIVES AND SYNTHETIC METHOD THEREOF - The present invention provides a chemical compound having the structure being one selected from a group consisting of | 03-21-2013 |
Patent application number | Description | Published |
20090101903 | Thin film transistor and method for manufaturing thereof - A thin-film transistor (TFT) includes a gate electrode, a gate dielectric layer, a semiconductor layer, source/drain electrodes, a passivation layer and a protection layer. The gate electrode is disposed on a substrate. The gate dielectric layer covers the gate electrode and the substrate. The semiconductor layer is disposed on the gate dielectric layer and above the gate electrode. The semiconductor layer has a channel region disposed above the gate electrode and source/drain regions disposed at both sides of the channel region. The source/drain electrodes are disposed on the source/drain regions of the semiconductor layer and each has a barrier layer disposed on the source/drain regions of the semiconductor layer and a conductive layer disposed on the barrier layer. The passivation layer is disposed over the surface of the source/drain electrodes. The protection layer is disposed over the substrate, the passivation layer, and the channel region of the semiconductor layer. | 04-23-2009 |
20110014788 | Display panel structure and manufacture method thereof - A display panel structure having a circuit element disposed thereon and method of manufacture are provided. The display panel includes a substrate and the circuit element disposed on the substrate. The circuit element has a first interface layer and a first conductive layer. Both the first interface layer and the first conductive layer have cooper materials. The material which makes the first interface layer includes a reactant or a compound of the material which makes the first conductive layer. The method for manufacturing includes the following steps: forming a first interface layer on the substrate; forming a first conductive layer on the first interface layer; and etching the first conductive and interface layers to form a pattern. The existence of the first interface reduces the penetration of the first conductive layer on the substrate and improves the adhesive force between the first conductive layer and the substrate. | 01-20-2011 |
20110147733 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device structure on a substrate and a manufacture method thereof is provided. The semiconductor device structure includes an oxide semiconductor transistor and a passivation layer containing free hydrogen. The semiconductor device structure is formed by following steps. A gate electrode is formed on the substrate. A gate dielectric layer covers the gate electrode. A source electrode is formed on the gate dielectric layer. A drain electrode is formed on the gate dielectric layer and separated from the source electrode and thereby forming a channel distance. An oxide semiconductor layer is formed on the gate dielectric layer, the source electrode and the drain electrode and between the source electrode and the drain electrode. The oxide semiconductor layer is further electrically connected with the source electrode and the drain electrode. A passivation layer covers the oxide semiconductor layer, the source electrode and the drain electrode. The passivation layer has a groove formed therein, and the groove surrounds the oxide semiconductor layer. | 06-23-2011 |
Patent application number | Description | Published |
20090057668 | Display Element and Method of Manufacturing the Same - A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer. | 03-05-2009 |
20090153056 | PIXEL STRUCTURE, DISPLAY PANEL, ELETRO-OPTICAL APPARATUS, AND METHOD THEREROF - A pixel structure disposed on a substrate including a thin film transistor (TFT), a bottom capacitor electrode, a dielectric layer, an upper capacitor electrode, a passivation layer, and a pixel electrode is provided. The TFT having a source/drain and the bottom capacitor electrode are disposed on the substrate. The dielectric layer is disposed on the bottom capacitor electrode. The upper capacitor electrode has a semiconductor layer, a barrier layer, and a metal layer. The semiconductor layer is disposed on the dielectric layer above the bottom capacitor electrode. The barrier layer is disposed on the semiconductor layer. The metal layer whose material includes copper, a copper alloy, or a combination thereof is disposed on the barrier layer. The passivation layer covers the TFT and the upper capacitor electrode and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening. | 06-18-2009 |
20090173944 | THIN FILM TRANSISTOR, ACTIVE DEVICE ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL - A thin film transistor (TFT) includes a substrate, a gate, a gate dielectric layer, a channel layer, a source and a drain. The gate and the gate dielectric layer are disposed on the substrate and the gate dielectric layer covers the gate. The channel layer is disposed on the gate dielectric layer over the gate, and the source and the drain are respectively disposed on a portion of the channel layer at both sides of the gate. At least one of the gate, the source and the drain has a lower conductive layer, an upper conductive layer and an intermediate conductive layer located between the lower conductive layer and the upper conductive layer. The material of the lower conductive layer is different from the material of the intermediate conductive layer, and the thickness of the lower conductive layer is less than or equal to about 150 Å. | 07-09-2009 |
20100038645 | Display Element and Method of Manufacturing the Same - A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer. | 02-18-2010 |
20120261755 | PIXEL STRUCTURE, DISPLAY PANEL, ELECTRO-OPTICAL APPARATUS, AND METHOD THEREOF - A pixel structure disposed on a substrate including a thin film transistor (TFT), a passivation layer, and a pixel electrode is provided. The TFT includes a gate, a dielectric layer, a channel layer, and a source/drain sequentially disposed on the substrate. The source/drain is disposed on a portion of the channel layer and has a semiconductor layer, a barrier layer and a metal layer. The barrier layer is disposed on a portion of the semiconductor layer. The metal layer is disposed on the barrier layer. The barrier layer is in contact with the semiconductor layer and the metal layer. Both of the metal layer and the barrier layer are positioned within a projection area of the semiconductor layer. The passivation layer covers the TFT and the dielectric layer and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening. | 10-18-2012 |
Patent application number | Description | Published |
20090053438 | Airtight ball and a method of fabricating the airtight ball - An airtight ball has an inner bladder, a sealing layer, a wound layer, a rubber layer and an outer leather covering. The inner bladder is a hollow, resilient sphere and has an inner space and an outer surface. The sealing layer is applied to the outer surface of the inner bladder and has a rubber glue layer, a polyvinyl alcohol (PVOH) layer and a rubber balloon. The rubber glue layer fills in air bubbles or holes formed in the outer surface of the inner bladder. The a PVOH layer forms a thin, airtight membrane on the rubber glue layer, keeps air from leaking out of the inner space of the inner bladder and further maintains roundness and increases bouncing ability of the ball. The rubber balloon is a thin layer of rubber attached to the PVOH layer. The wound layer is wound around the rubber balloon that keeps the wound layer from cutting the PVOH and stabilizes the wound layer. The present invention not only prevents air leakage but also increases the ball's roundness and strength. | 02-26-2009 |
20140080643 | LEAK-FREE AMERICAN FOOTBALL - Provided is a leak-free American football, which has a polyurethane foam having a shape of an American football; a covering formed on an exterior surface of the polyurethane foam and having a seam; multiple pairs of lacing holes formed in the covering along two opposite sides of the seam, and a lace passing through the multiple pairs of the lacing holes to close the seam, such that the polyurethane foam is covered by the covering and the lace. Since the polyurethane foam is solid and elastic, the leak-free American football can maintain a desired size, shape and bounce without the need for inflation, thereby improving the stability and durability. | 03-20-2014 |
20140087900 | TYPE TWO-LAYER LEAK-PROOF BALL AND MANUFACTURING METHOD THEREOF - A two-layer leak-proof ball comprises a sheath layer ( | 03-27-2014 |
Patent application number | Description | Published |
20110228502 | ACTIVE DEVICE ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF - An active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°. | 09-22-2011 |
20120270392 | FABRICATING METHOD OF ACTIVE DEVICE ARRAY SUBSTRATE - A fabricating method of an active device array substrate is provided. The active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°. | 10-25-2012 |
20130119371 | ACTIVE DEVICE - An active device including a source, a drain, an oxide semiconductor layer, a gate and a gate insulator layer is provided. The source includes first stripe electrodes parallel to each other and a first connection electrode connected thereto. The drain includes second stripe electrodes parallel to each other and a second connection electrode connected thereto, wherein the first stripe electrodes and the second stripe electrodes are parallel to each other, electrically isolated, and alternately arranged, and a zigzag trench is formed therebetween. The gate extends along the zigzag trench. The oxide semiconductor layer is in contact with the source and drain, wherein a contact area among the oxide semiconductor layer and each first stripe electrodes substantially equals to a layout area of each first stripe electrodes and a contact area among each second stripe electrodes substantially equals to a layout area of each second stripe electrodes. | 05-16-2013 |
20130134489 | PIXEL STRUCTURE AND FABRICATING METHOD THEREOF - A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first patterned metal layer. The metal layer and the semiconductor layer are patterned to form a second patterned metal layer and a patterned semiconductor layer. The second patterned metal layer includes data lines, a source and a drain. The patterned semiconductor layer includes a first semiconductor pattern completely overlapping the second patterned metal layer and a second semiconductor pattern without overlapping the second patterned metal layer, wherein the second semiconductor pattern includes a channel pattern and a marginal pattern. The channel pattern is between the source and the drain and the marginal pattern surrounds the first semiconductor pattern. | 05-30-2013 |
20130168682 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a channel layer, a gate insulation layer, a source, a drain and a silicon-aluminum-oxide layer. The gate is disposed on a substrate. The channel layer is disposed on the substrate. The channel layer overlaps the gate. The gate insulation layer is disposed between the gate and the channel layer. The source and the drain are disposed on two sides of the channel layer. The silicon-aluminum-oxide layer is disposed on the substrate and covers the source, the drain and the channel layer. | 07-04-2013 |
20130328069 | ACTIVE DEVICE, DRIVING CIRCUIT STRUCTURE, AND DISPLAY PANEL - An active device, a driving circuit structure, and a display panel are provided. The active device includes a gate, a gate insulation layer covering the gate, a semiconductor layer disposed above the gate, an etching stop layer disposed on the gate insulation layer and the semiconductor layer, a source, and a drain. The gate forms a meandering pattern on a substrate. The semiconductor layer has an area substantially defining a device region where the active device is. The etching stop layer has a first contact opening and a second contact opening. The first contact opening and the second contact opening separated from each other and both exposing the semiconductor layer. The source and the drain separated from each other are disposed on the etching stop layer and in contact with the semiconductor layer through the first contact opening and the second contact opening, respectively. | 12-12-2013 |
20140291742 | PIXEL STRUCTURE AND FABRICATING METHOD THEREOF - A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first patterned metal layer. The metal layer and the semiconductor layer are patterned to form a second patterned metal layer and a patterned semiconductor layer. The second patterned metal layer includes data lines, a source and a drain. The patterned semiconductor layer includes a first semiconductor pattern completely overlapping the second patterned metal layer and a second semiconductor pattern without overlapping the second patterned metal layer, wherein the second semiconductor pattern includes a channel pattern and a marginal pattern. The channel pattern is between the source and the drain and the marginal pattern surrounds the first semiconductor pattern. | 10-02-2014 |