Patent application number | Description | Published |
20120024369 | PHOTO-CHEMICAL SOLAR CELL WITH NANONEEDLE ELECTRODE AND METHOD MANUFACTURING THE SAME - A photo-chemical solar cell with nanoneedle electrode and a method manufacturing the same includes at least a working electrode, a counter electrode, an electrolyte layer and a photosensitized dye layer. The working electrode is an nanoneedle electrode formed from an nanoneedle semiconductor layer, wherein the nanoneedle semiconductor layer is prepared by sol-gel method at a low temperature to increase the specific surface area, adsorb more dye, increase the conductive ratio of the electrode, and thus improve the photo-current and the conversion efficiency. | 02-02-2012 |
20120046480 | DENSE CU BASED THIN FILM AND THE MANUFACTURING PROCESS THEREOF - The disclosure provides a dense Cu thin film, a dense CuO thin film and the manufacturing process applied in metallization process of ultra-large scale integration (ULSI), which uses a two-step growth consisting of pre-deposition and annealing to form a dense Cu thin film or a dense CuO thin film. In the process, a copper-containing metal-organic complex is used as precursor and a reducing gas is used as carrier gas. The precursor is carried to a reactive system with a substrate by a carrier gas and pre-deposit a CuO thin film on the substrate under lower temperature. Next, stop supplying the precursor and raise the temperature or offer other energy to anneal the thin film with hydrogen gas or reducing gas, which reduces the CuO thin film to a smooth and dense Cu thin film. Then, choosing oxide containing gas as the react gas obtains the CuO thin film. | 02-23-2012 |
20120118204 | METHOD FOR PREPARING LOW K MATERIAL AND FILM THEREOF - A method for preparing a low dielectric constant (low k) material and a film thereof is provided. The method includes the following steps. A substrate is first put into a plasma generating reaction system, and a carrier gas carrying a carbon and fluorine containing silicon dioxide precursor is then introduced into the plasma generating reaction system, so that the carbon and fluorine containing silicon dioxide precursor is formed on the substrate. After that, the carbon and fluorine containing silicon dioxide precursor is converted to a low k material film through heating; meanwhile, a stress of the low k material film is eliminated such that the film has a more compact structure. By means of these steps the carbon and fluorine containing silicon dioxide precursor is still capable of forming a low k material film of silicon dioxide containing a large amount of fluorocarbon, even under various different atmospheres. | 05-17-2012 |
20130143402 | Method of forming Cu thin film - The disclosure provides a method for forming a dense Cu thin film by atomic layer deposition, comprising the following steps of: (A) providing an additive gas; (B) choosing a copper-containing metal-organic complex as a precursor; (C) using a carrier gas to introduce the additive gas into the precursor cell mixing with the precursor; (D) pre-depositing the precursor on the surface of the substrate with a TaN | 06-06-2013 |
20140072479 | Delivery Equipment for the Solid Precursor Particles - The present invention discloses a delivery equipment for the solid precursor particles, which is applied to the deposition of thin film. The delivery equipment for the solid precursor particles mainly comprises a container, a feeding material inlet, a feeding material tube, a feeding gas inlet, a feeding gas tube, and an output. A plurality of solid precursor particles are stored in the carrier liquid of the container, and then heated to be vapor, removed through the output of the container. The solid precursor particles are prepared by sublimation or grounding and uniformly dispersed in the carrier liquid. The disclosed delivery equipment for the solid precursor particles can reduce the required heating temperature, increase the thermal stability, prolong the used life time, and then increase the using efficiency of the precursors. | 03-13-2014 |
Patent application number | Description | Published |
20100171207 | STACKABLE SEMICONDUCTOR DEVICE PACKAGES - In one embodiment, a manufacturing method includes: (1) applying a first electrically conductive material to an upper surface of a substrate to form first conductive bumps; (2) electrically connecting a semiconductor device to the upper surface of the substrate; (3) applying a molding material to form a molded structure covering the first conductive bumps and the semiconductor device, upper ends of the first conductive bumps being recessed below an upper surface of the molded structure; (4) forming openings adjacent to the upper surface of the molded structure, the openings exposing the upper ends of the first conductive bumps; (5) applying, through the openings, a second electrically conductive material to form second conductive bumps; and (6) forming cutting slits extending through the molded structure and the substrate. | 07-08-2010 |
20110156251 | Semiconductor Package - The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least one opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors. Whereby, the solder mask contacts the first pads directly, and thus results in higher bonding strength, so as to avoid the bridge between the first conductors caused by the first conductors permeating into the interface between the solder mask and the first pads. | 06-30-2011 |
20130161816 | SEMICONDUCTOR PACKAGE - The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least on opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors. Whereby, the solder mask contacts the first pads directly, and thus results in higher bonding strength, so as to avoid the bridge between the first conductors caused by the first conductors permeating into the interface between the solder mask and the first pads. | 06-27-2013 |
Patent application number | Description | Published |
20090023255 | Method for Reshaping Silicon Surfaces with Shallow Trench Isolation - A method for making a semiconductor device by reshaping a silicon surface with a sacrificial layer is presented. In the present invention the steps of forming a sacrificial dielectric layer and removing the sacrificial dielectric layer are repeated multiple times in order to remove sharp edges from the silicon surface near the field oxides. Another aspect of the present invention includes making a MOSFET transistor that incorporates the forming and removing of multiple sacrificial layers into the process. | 01-22-2009 |
20110309417 | Method for Reshaping Silicon Surfaces with Shallow Trench Isolation - A method for making a semiconductor device by reshaping a silicon surface with a sacrificial layer is presented. In the present invention the steps of forming a sacrificial dielectric layer and removing the sacrificial dielectric layer are repeated multiple times in order to remove sharp edges from the silicon surface near the field oxides. Another aspect of the present invention includes making a MOSFET transistor that incorporates the forming and removing of multiple sacrificial layers into the process. | 12-22-2011 |
20140151782 | Methods and Apparatus for Non-Volatile Memory Cells with Increased Programming Efficiency - Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided. | 06-05-2014 |
20140203236 | ONE TRANSISTOR AND ONE RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE WITH SPACER - The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode; a spacer surrounding the capping layer; and, a top electrode on the capping layer having a smaller width than the resistive material layer. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer. | 07-24-2014 |
20140252295 | ONE TRANSISTOR AND ONE RESISTIVE (1T1R) RANDOM ACCESS MEMORY (RRAM) STRUCTURE WITH DUAL SPACERS - The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode, a first spacer surrounding the capping layer and a top electrode, a second spacer surround the top portion of the bottom electrode and the first spacer, and the top electrode. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer. | 09-11-2014 |
20140254237 | Method for Operating RRAM Memory - Methods for operating memory are disclosed. A method includes applying a select word line voltage to a word line node of a first resistive random access memory (RRAM) cell; applying a first programming voltage to a source line node of the first RRAM cell; and setting the first RRAM cell comprising applying a second programming voltage to a bit line node of the first RRAM cell. The first programming voltage is greater than zero volts, and the second programming voltage is greater than the first programming voltage. Other disclosed methods include concurrently setting and resetting RRAM cells. | 09-11-2014 |
20140264229 | LOW FORM VOLTAGE RESISTIVE RANDOM ACCESS MEMORY (RRAM) - The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion. | 09-18-2014 |
20150085558 | DEVICE AND METHOD FOR FORMING RESISTIVE RANDOM ACCESS MEMORY CELL - A device and method for forming resistive random access memory cell are provided. The method includes: providing a first voltage to a first word line connected to a first RRAM cell to form the first RRAM cell; and providing a negative voltage to a second word line connected to a second RRAM cell that shares a first source line and a first bit line with the first RRAM cell. An exemplary device includes: a first RRAM cell, a second RRAM cell, a first voltage source and a charge pump circuit. The first RRAM cell is connected to a first word line. The second RRAM cell is connected to a second word line. The first voltage source provides a first voltage to the first word line to form the first RRAM cell. The charge pump circuit provides a negative voltage to the second word line. | 03-26-2015 |
Patent application number | Description | Published |
20090279306 | Lighting Apparatus - A lighting apparatus is disclosed. The lighting apparatus comprises a casing, at least one light source and a microstructure cover. The light source is disposed on one side of the casing. The microstructure cover is mounted on the casing opposite to the reflective face thereof. The microstructure cover has a plurality of guiding micro-structures to guide light and a plurality of dispersing micro-structures to disperse light. | 11-12-2009 |
20130271953 | ILLUMINATION MODULE - An illumination module is provided, and includes a case, a light-transmitting window and a light source module. The case includes a top plate having an opening. The light-transmitting window covers the opening of the top plate. The light source module includes a light guide element, a first reflective sheet, a second reflective sheet, at least one light source and a fluorescence member. The light guide element includes a light incident surface, a light-exiting surface, a first reflective surface and a second reflective surface. The first reflective sheet and the second reflective sheet are disposed on the first reflective surface and the second reflective surface respectively. A light-emitting surface of the light source faces the light incident surface of the light guide element. At least one section of the fluorescence member faces the light-exiting surface of the light guide element. | 10-17-2013 |
20130272029 | LIGHT SOURCE MODULE - A light source module is provided. The light source module includes a light guide element, at least one light source and a fluorescence member. The light guide element includes a light incident surface and a light-exiting surface. The light-exiting surface is opposite to the light incident surface. A light-emitting surface of the at least one light source faces the light incident surface of the light guide element. At least one section of the fluorescence member faces the light-exiting surface of the light guide element. | 10-17-2013 |