Patent application number | Description | Published |
20100153818 | MULTILEVEL ENCODING WITH ERROR CORRECTION - Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of multilevel memory cells by level-shifting a subset of the plurality of multilevel memory cells for a bit of the plurality of bits. Other embodiments may be described and claimed. | 06-17-2010 |
20100269017 | NON-VOLATILE MEMORY WITH EXTENDED ERROR CORRECTION PROTECTION - Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity values of data values stored in a plurality of codewords of an NVM device. Other embodiments may be described and claimed. | 10-21-2010 |
20100293434 | NON-VOLATILE MEMORY WITH BI-DIRECTIONAL ERROR CORRECTION PROTECTION - Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with bi-directional error correction protection. In some embodiments, multiple multi-level parity cells are used to represent parity values stored in codewords of an NVM device. Other embodiments may be described and claimed. | 11-18-2010 |
20120137195 | PRESERVING DATA INTEGRITY IN A MEMORY SYSTEM - A method includes detecting that a first device in a memory array has degraded, the first device storing a portion of a data record, wherein the data record is encoded using a first error control technique. The method continues with recovering the data record using portions of the data record stored in devices other than the first device in the memory array and encoding the data record using a second error control technique. The method also includes storing the data record in the devices of the memory array other than the first device. | 05-31-2012 |
20120173793 | MEMORY DEVICE USING EXTENDED INTERFACE COMMANDS - A memory device includes a serial interface buffer that receives a hardware-decodable command and an extended interface command. The memory device also includes a logic module that directs the hardware-decodable command to a register for execution by a microcontroller. The logic module additionally loads a command received following the extended interface command into a sub-op-code register, wherein the logic module remains passive after loading the command received following the extended interface command into the sub-op-code register. Also included is a microcontroller that interprets the command in the sub-op-code register. | 07-05-2012 |
20120221917 | ERROR CONTROL IN MEMORY STORAGE SYSTEMS - A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors. | 08-30-2012 |
20130024749 | MULTILEVEL ENCODING WITH ERROR CORRECTION - Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by responding to bits of the plurality of bits by changing the logic levels of corresponding groups of memory cells of the plurality of memory cells. Other embodiments may be described and claimed. | 01-24-2013 |
20130080856 | NON-VOLATILE MEMORY WITH EXTENDED ERROR CORRECTION PROTECTION - Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity values of data values stored in a plurality of codewords of an NVM device. Other embodiments may be described and claimed. | 03-28-2013 |
20130311853 | NON-VOLATILE MEMORY WITH EXTENDED ERROR CORRECTION PROTECTION - Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity values of data values stored in a plurality of codewords of an NVM device. Other embodiments may be described and claimed. | 11-21-2013 |
20130326304 | ERROR DETECTION OR CORRECTION OF A PORTION OF A CODEWORD IN A MEMORY DEVICE - Example embodiments described herein may relate error detection and correction on a portion of a codeword in a memory device. | 12-05-2013 |
20140129872 | ERROR CONTROL IN MEMORY STORAGE SYSTEMS - A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors. | 05-08-2014 |
20140173383 | MULTILEVEL ENCODING WITH ERROR CORRECTION - Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by responding to bits of the plurality of bits by changing the logic levels of corresponding groups of memory cells of the plurality of memory cells. Other embodiments may be described and claimed. | 06-19-2014 |
20140359169 | MEMORY DEVICE USING EXTENDED INTERFACE COMMANDS - A memory device includes a serial interface buffer that receives a hardware-decodable command and an extended interface command. The memory device also includes a logic module that directs the hardware-decodable command to a register for execution by a microcontroller. The logic module additionally loads a command received following the extended interface command into a sub-op-code register, wherein the logic module remains passive after loading the command received following the extended interface command into the sub-op-code register. Also included is a microcontroller that interprets the command in the sub-op-code register. | 12-04-2014 |